forked from OSchip/llvm-project
533 lines
23 KiB
TableGen
533 lines
23 KiB
TableGen
//===-- FLATInstructions.td - FLAT Instruction Defintions -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def FLATAtomic : ComplexPattern<i64, 2, "SelectFlat">;
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//===----------------------------------------------------------------------===//
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// FLAT classes
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//===----------------------------------------------------------------------===//
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class FLAT_Pseudo<string opName, dag outs, dag ins,
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string asmOps, list<dag> pattern=[]> :
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InstSI<outs, ins, "", pattern>,
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SIMCInstr<opName, SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let SubtargetPredicate = isCIVI;
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let FLAT = 1;
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// Internally, FLAT instruction are executed as both an LDS and a
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// Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
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// and are not considered done until both have been decremented.
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let VM_CNT = 1;
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let LGKM_CNT = 1;
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let Uses = [EXEC, FLAT_SCR]; // M0
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let UseNamedOperandTable = 1;
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let hasSideEffects = 0;
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let SchedRW = [WriteVMEM];
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string Mnemonic = opName;
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string AsmOperands = asmOps;
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bits<1> has_vdst = 1;
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bits<1> has_data = 1;
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bits<1> has_glc = 1;
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bits<1> glcValue = 0;
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}
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class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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Enc64 {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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// copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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// encoding fields
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bits<8> vaddr;
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bits<8> vdata;
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bits<8> vdst;
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bits<1> slc;
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bits<1> glc;
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// We don't use tfe right now, and it was removed in gfx9.
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bits<1> tfe = 0;
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// 15-0 is reserved.
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let Inst{16} = !if(ps.has_glc, glc, ps.glcValue);
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let Inst{17} = slc;
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let Inst{24-18} = op;
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let Inst{31-26} = 0x37; // Encoding.
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let Inst{39-32} = vaddr;
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let Inst{47-40} = !if(ps.has_data, vdata, ?);
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// 54-48 is reserved.
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let Inst{55} = tfe;
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let Inst{63-56} = !if(ps.has_vdst, vdst, ?);
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}
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class FLAT_Load_Pseudo <string opName, RegisterClass regClass> : FLAT_Pseudo<
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opName,
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(outs regClass:$vdst),
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(ins VReg_64:$vaddr, GLC:$glc, slc:$slc),
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" $vdst, $vaddr$glc$slc"> {
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let has_data = 0;
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let mayLoad = 1;
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}
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class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass> : FLAT_Pseudo<
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opName,
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(outs),
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(ins VReg_64:$vaddr, vdataClass:$vdata, GLC:$glc, slc:$slc),
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" $vaddr, $vdata$glc$slc"> {
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let mayLoad = 0;
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let mayStore = 1;
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let has_vdst = 0;
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}
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multiclass FLAT_Atomic_Pseudo<
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string opName,
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RegisterClass vdst_rc,
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc> {
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def "" : FLAT_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc),
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" $vaddr, $vdata$slc",
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[]>,
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AtomicNoRet <NAME, 0> {
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let mayLoad = 1;
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let mayStore = 1;
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let has_glc = 0;
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let glcValue = 0;
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let has_vdst = 0;
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let PseudoInstr = NAME;
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}
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def _RTN : FLAT_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc),
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" $vdst, $vaddr, $vdata glc$slc",
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[(set vt:$vdst,
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(atomic (FLATAtomic i64:$vaddr, i1:$slc), data_vt:$vdata))]>,
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AtomicNoRet <NAME, 1> {
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let mayLoad = 1;
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let mayStore = 1;
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let hasPostISelHook = 1;
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let has_glc = 0;
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let glcValue = 1;
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let PseudoInstr = NAME # "_RTN";
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}
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}
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class flat_binary_atomic_op<SDNode atomic_op> : PatFrag<
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(ops node:$ptr, node:$value),
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(atomic_op node:$ptr, node:$value),
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[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.FLAT_ADDRESS;}]
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>;
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def atomic_cmp_swap_flat : flat_binary_atomic_op<AMDGPUatomic_cmp_swap>;
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def atomic_swap_flat : flat_binary_atomic_op<atomic_swap>;
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def atomic_add_flat : flat_binary_atomic_op<atomic_load_add>;
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def atomic_and_flat : flat_binary_atomic_op<atomic_load_and>;
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def atomic_max_flat : flat_binary_atomic_op<atomic_load_max>;
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def atomic_min_flat : flat_binary_atomic_op<atomic_load_min>;
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def atomic_or_flat : flat_binary_atomic_op<atomic_load_or>;
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def atomic_sub_flat : flat_binary_atomic_op<atomic_load_sub>;
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def atomic_umax_flat : flat_binary_atomic_op<atomic_load_umax>;
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def atomic_umin_flat : flat_binary_atomic_op<atomic_load_umin>;
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def atomic_xor_flat : flat_binary_atomic_op<atomic_load_xor>;
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def atomic_inc_flat : flat_binary_atomic_op<SIatomic_inc>;
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def atomic_dec_flat : flat_binary_atomic_op<SIatomic_dec>;
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//===----------------------------------------------------------------------===//
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// Flat Instructions
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//===----------------------------------------------------------------------===//
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def FLAT_LOAD_UBYTE : FLAT_Load_Pseudo <"flat_load_ubyte", VGPR_32>;
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def FLAT_LOAD_SBYTE : FLAT_Load_Pseudo <"flat_load_sbyte", VGPR_32>;
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def FLAT_LOAD_USHORT : FLAT_Load_Pseudo <"flat_load_ushort", VGPR_32>;
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def FLAT_LOAD_SSHORT : FLAT_Load_Pseudo <"flat_load_sshort", VGPR_32>;
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def FLAT_LOAD_DWORD : FLAT_Load_Pseudo <"flat_load_dword", VGPR_32>;
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def FLAT_LOAD_DWORDX2 : FLAT_Load_Pseudo <"flat_load_dwordx2", VReg_64>;
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def FLAT_LOAD_DWORDX4 : FLAT_Load_Pseudo <"flat_load_dwordx4", VReg_128>;
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def FLAT_LOAD_DWORDX3 : FLAT_Load_Pseudo <"flat_load_dwordx3", VReg_96>;
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def FLAT_STORE_BYTE : FLAT_Store_Pseudo <"flat_store_byte", VGPR_32>;
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def FLAT_STORE_SHORT : FLAT_Store_Pseudo <"flat_store_short", VGPR_32>;
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def FLAT_STORE_DWORD : FLAT_Store_Pseudo <"flat_store_dword", VGPR_32>;
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def FLAT_STORE_DWORDX2 : FLAT_Store_Pseudo <"flat_store_dwordx2", VReg_64>;
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def FLAT_STORE_DWORDX4 : FLAT_Store_Pseudo <"flat_store_dwordx4", VReg_128>;
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def FLAT_STORE_DWORDX3 : FLAT_Store_Pseudo <"flat_store_dwordx3", VReg_96>;
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defm FLAT_ATOMIC_CMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap",
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VGPR_32, i32, atomic_cmp_swap_flat,
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v2i32, VReg_64>;
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defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap_x2",
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VReg_64, i64, atomic_cmp_swap_flat,
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v2i64, VReg_128>;
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defm FLAT_ATOMIC_SWAP : FLAT_Atomic_Pseudo <"flat_atomic_swap",
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VGPR_32, i32, atomic_swap_flat>;
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defm FLAT_ATOMIC_SWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_swap_x2",
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VReg_64, i64, atomic_swap_flat>;
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defm FLAT_ATOMIC_ADD : FLAT_Atomic_Pseudo <"flat_atomic_add",
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VGPR_32, i32, atomic_add_flat>;
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defm FLAT_ATOMIC_SUB : FLAT_Atomic_Pseudo <"flat_atomic_sub",
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VGPR_32, i32, atomic_sub_flat>;
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defm FLAT_ATOMIC_SMIN : FLAT_Atomic_Pseudo <"flat_atomic_smin",
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VGPR_32, i32, atomic_min_flat>;
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defm FLAT_ATOMIC_UMIN : FLAT_Atomic_Pseudo <"flat_atomic_umin",
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VGPR_32, i32, atomic_umin_flat>;
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defm FLAT_ATOMIC_SMAX : FLAT_Atomic_Pseudo <"flat_atomic_smax",
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VGPR_32, i32, atomic_max_flat>;
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defm FLAT_ATOMIC_UMAX : FLAT_Atomic_Pseudo <"flat_atomic_umax",
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VGPR_32, i32, atomic_umax_flat>;
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defm FLAT_ATOMIC_AND : FLAT_Atomic_Pseudo <"flat_atomic_and",
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VGPR_32, i32, atomic_and_flat>;
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defm FLAT_ATOMIC_OR : FLAT_Atomic_Pseudo <"flat_atomic_or",
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VGPR_32, i32, atomic_or_flat>;
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defm FLAT_ATOMIC_XOR : FLAT_Atomic_Pseudo <"flat_atomic_xor",
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VGPR_32, i32, atomic_xor_flat>;
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defm FLAT_ATOMIC_INC : FLAT_Atomic_Pseudo <"flat_atomic_inc",
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VGPR_32, i32, atomic_inc_flat>;
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defm FLAT_ATOMIC_DEC : FLAT_Atomic_Pseudo <"flat_atomic_dec",
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VGPR_32, i32, atomic_dec_flat>;
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defm FLAT_ATOMIC_ADD_X2 : FLAT_Atomic_Pseudo <"flat_atomic_add_x2",
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VReg_64, i64, atomic_add_flat>;
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defm FLAT_ATOMIC_SUB_X2 : FLAT_Atomic_Pseudo <"flat_atomic_sub_x2",
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VReg_64, i64, atomic_sub_flat>;
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defm FLAT_ATOMIC_SMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_smin_x2",
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VReg_64, i64, atomic_min_flat>;
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defm FLAT_ATOMIC_UMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_umin_x2",
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VReg_64, i64, atomic_umin_flat>;
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defm FLAT_ATOMIC_SMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_smax_x2",
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VReg_64, i64, atomic_max_flat>;
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defm FLAT_ATOMIC_UMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_umax_x2",
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VReg_64, i64, atomic_umax_flat>;
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defm FLAT_ATOMIC_AND_X2 : FLAT_Atomic_Pseudo <"flat_atomic_and_x2",
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VReg_64, i64, atomic_and_flat>;
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defm FLAT_ATOMIC_OR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_or_x2",
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VReg_64, i64, atomic_or_flat>;
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defm FLAT_ATOMIC_XOR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_xor_x2",
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VReg_64, i64, atomic_xor_flat>;
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defm FLAT_ATOMIC_INC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_inc_x2",
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VReg_64, i64, atomic_inc_flat>;
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defm FLAT_ATOMIC_DEC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_dec_x2",
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VReg_64, i64, atomic_dec_flat>;
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let SubtargetPredicate = isCI in { // CI Only flat instructions : FIXME Only?
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defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap",
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VGPR_32, f32, null_frag, v2f32, VReg_64>;
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defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap_x2",
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VReg_64, f64, null_frag, v2f64, VReg_128>;
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defm FLAT_ATOMIC_FMIN : FLAT_Atomic_Pseudo <"flat_atomic_fmin",
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VGPR_32, f32>;
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defm FLAT_ATOMIC_FMAX : FLAT_Atomic_Pseudo <"flat_atomic_fmax",
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VGPR_32, f32>;
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defm FLAT_ATOMIC_FMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2",
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VReg_64, f64>;
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defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2",
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VReg_64, f64>;
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} // End SubtargetPredicate = isCI
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//===----------------------------------------------------------------------===//
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// Flat Patterns
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//===----------------------------------------------------------------------===//
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class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr),
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(ld node:$ptr), [{
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auto const AS = cast<MemSDNode>(N)->getAddressSpace();
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return AS == AMDGPUASI.FLAT_ADDRESS ||
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AS == AMDGPUASI.GLOBAL_ADDRESS ||
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AS == AMDGPUASI.CONSTANT_ADDRESS;
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}]>;
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class flat_st <SDPatternOperator st> : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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auto const AS = cast<MemSDNode>(N)->getAddressSpace();
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return AS == AMDGPUASI.FLAT_ADDRESS ||
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AS == AMDGPUASI.GLOBAL_ADDRESS;
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}]>;
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def atomic_flat_load : flat_ld <atomic_load>;
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def flat_load : flat_ld <load>;
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def flat_az_extloadi8 : flat_ld <az_extloadi8>;
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def flat_sextloadi8 : flat_ld <sextloadi8>;
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def flat_az_extloadi16 : flat_ld <az_extloadi16>;
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def flat_sextloadi16 : flat_ld <sextloadi16>;
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def atomic_flat_store : flat_st <atomic_store>;
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def flat_store : flat_st <store>;
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def flat_truncstorei8 : flat_st <truncstorei8>;
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def flat_truncstorei16 : flat_st <truncstorei16>;
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// Patterns for global loads with no offset.
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class FlatLoadPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
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(vt (node i64:$addr)),
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(inst $addr, 0, 0)
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>;
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class FlatLoadAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
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(vt (node i64:$addr)),
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(inst $addr, 1, 0)
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>;
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class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
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(node vt:$data, i64:$addr),
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(inst $addr, $data, 0, 0)
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>;
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class FlatStoreAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
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// atomic store follows atomic binop convention so the address comes
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// first.
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(node i64:$addr, vt:$data),
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(inst $addr, $data, 1, 0)
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>;
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class FlatAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,
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ValueType data_vt = vt> : Pat <
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(vt (node i64:$addr, data_vt:$data)),
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(inst $addr, $data, 0)
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>;
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let Predicates = [isCIVI] in {
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def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i32>;
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def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i32>;
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def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i16>;
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def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i16>;
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def : FlatLoadPat <FLAT_LOAD_USHORT, flat_az_extloadi16, i32>;
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def : FlatLoadPat <FLAT_LOAD_SSHORT, flat_sextloadi16, i32>;
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def : FlatLoadPat <FLAT_LOAD_DWORD, flat_load, i32>;
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def : FlatLoadPat <FLAT_LOAD_DWORDX2, flat_load, v2i32>;
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def : FlatLoadPat <FLAT_LOAD_DWORDX4, flat_load, v4i32>;
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def : FlatLoadAtomicPat <FLAT_LOAD_DWORD, atomic_flat_load, i32>;
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def : FlatLoadAtomicPat <FLAT_LOAD_DWORDX2, atomic_flat_load, i64>;
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def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i32>;
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def : FlatStorePat <FLAT_STORE_SHORT, flat_truncstorei16, i32>;
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def : FlatStorePat <FLAT_STORE_DWORD, flat_store, i32>;
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def : FlatStorePat <FLAT_STORE_DWORDX2, flat_store, v2i32>;
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def : FlatStorePat <FLAT_STORE_DWORDX4, flat_store, v4i32>;
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def : FlatStoreAtomicPat <FLAT_STORE_DWORD, atomic_flat_store, i32>;
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def : FlatStoreAtomicPat <FLAT_STORE_DWORDX2, atomic_flat_store, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_ADD_RTN, atomic_add_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_SUB_RTN, atomic_sub_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_INC_RTN, atomic_inc_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_DEC_RTN, atomic_dec_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_AND_RTN, atomic_and_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_SMAX_RTN, atomic_max_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_UMAX_RTN, atomic_umax_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_SMIN_RTN, atomic_min_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_UMIN_RTN, atomic_umin_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_OR_RTN, atomic_or_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_SWAP_RTN, atomic_swap_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_RTN, AMDGPUatomic_cmp_swap_global, i32, v2i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_XOR_RTN, atomic_xor_global, i32>;
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def : FlatAtomicPat <FLAT_ATOMIC_ADD_X2_RTN, atomic_add_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_SUB_X2_RTN, atomic_sub_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_INC_X2_RTN, atomic_inc_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_DEC_X2_RTN, atomic_dec_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_AND_X2_RTN, atomic_and_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_SMAX_X2_RTN, atomic_max_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_UMAX_X2_RTN, atomic_umax_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_SMIN_X2_RTN, atomic_min_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_UMIN_X2_RTN, atomic_umin_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_OR_X2_RTN, atomic_or_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_SWAP_X2_RTN, atomic_swap_global, i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_X2_RTN, AMDGPUatomic_cmp_swap_global, i64, v2i64>;
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def : FlatAtomicPat <FLAT_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
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} // End Predicates = [isCIVI]
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let Predicates = [isVI] in {
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def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i16>;
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def : FlatStorePat <FLAT_STORE_SHORT, flat_store, i16>;
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}
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//===----------------------------------------------------------------------===//
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// Target
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// CI
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//===----------------------------------------------------------------------===//
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class FLAT_Real_ci <bits<7> op, FLAT_Pseudo ps> :
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FLAT_Real <op, ps>,
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SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
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let AssemblerPredicate = isCIOnly;
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let DecoderNamespace="CI";
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}
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def FLAT_LOAD_UBYTE_ci : FLAT_Real_ci <0x8, FLAT_LOAD_UBYTE>;
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def FLAT_LOAD_SBYTE_ci : FLAT_Real_ci <0x9, FLAT_LOAD_SBYTE>;
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def FLAT_LOAD_USHORT_ci : FLAT_Real_ci <0xa, FLAT_LOAD_USHORT>;
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def FLAT_LOAD_SSHORT_ci : FLAT_Real_ci <0xb, FLAT_LOAD_SSHORT>;
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def FLAT_LOAD_DWORD_ci : FLAT_Real_ci <0xc, FLAT_LOAD_DWORD>;
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def FLAT_LOAD_DWORDX2_ci : FLAT_Real_ci <0xd, FLAT_LOAD_DWORDX2>;
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def FLAT_LOAD_DWORDX4_ci : FLAT_Real_ci <0xe, FLAT_LOAD_DWORDX4>;
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def FLAT_LOAD_DWORDX3_ci : FLAT_Real_ci <0xf, FLAT_LOAD_DWORDX3>;
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def FLAT_STORE_BYTE_ci : FLAT_Real_ci <0x18, FLAT_STORE_BYTE>;
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def FLAT_STORE_SHORT_ci : FLAT_Real_ci <0x1a, FLAT_STORE_SHORT>;
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def FLAT_STORE_DWORD_ci : FLAT_Real_ci <0x1c, FLAT_STORE_DWORD>;
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def FLAT_STORE_DWORDX2_ci : FLAT_Real_ci <0x1d, FLAT_STORE_DWORDX2>;
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def FLAT_STORE_DWORDX4_ci : FLAT_Real_ci <0x1e, FLAT_STORE_DWORDX4>;
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def FLAT_STORE_DWORDX3_ci : FLAT_Real_ci <0x1f, FLAT_STORE_DWORDX3>;
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multiclass FLAT_Real_Atomics_ci <bits<7> op, FLAT_Pseudo ps> {
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def _ci : FLAT_Real_ci<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
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def _RTN_ci : FLAT_Real_ci<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
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}
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defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_ci <0x30, FLAT_ATOMIC_SWAP>;
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defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_ci <0x31, FLAT_ATOMIC_CMPSWAP>;
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defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_ci <0x32, FLAT_ATOMIC_ADD>;
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defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_ci <0x33, FLAT_ATOMIC_SUB>;
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defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_ci <0x35, FLAT_ATOMIC_SMIN>;
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defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_ci <0x36, FLAT_ATOMIC_UMIN>;
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defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_ci <0x37, FLAT_ATOMIC_SMAX>;
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defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_ci <0x38, FLAT_ATOMIC_UMAX>;
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defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_ci <0x39, FLAT_ATOMIC_AND>;
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defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_ci <0x3a, FLAT_ATOMIC_OR>;
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defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_ci <0x3b, FLAT_ATOMIC_XOR>;
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defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_ci <0x3c, FLAT_ATOMIC_INC>;
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defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_ci <0x3d, FLAT_ATOMIC_DEC>;
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defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_ci <0x50, FLAT_ATOMIC_SWAP_X2>;
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defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_ci <0x51, FLAT_ATOMIC_CMPSWAP_X2>;
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defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_ci <0x52, FLAT_ATOMIC_ADD_X2>;
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defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_ci <0x53, FLAT_ATOMIC_SUB_X2>;
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defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_ci <0x55, FLAT_ATOMIC_SMIN_X2>;
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defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_ci <0x56, FLAT_ATOMIC_UMIN_X2>;
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defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_ci <0x57, FLAT_ATOMIC_SMAX_X2>;
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defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_ci <0x58, FLAT_ATOMIC_UMAX_X2>;
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defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_ci <0x59, FLAT_ATOMIC_AND_X2>;
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defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_ci <0x5a, FLAT_ATOMIC_OR_X2>;
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defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_ci <0x5b, FLAT_ATOMIC_XOR_X2>;
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defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_ci <0x5c, FLAT_ATOMIC_INC_X2>;
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|
defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_ci <0x5d, FLAT_ATOMIC_DEC_X2>;
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|
|
|
// CI Only flat instructions
|
|
defm FLAT_ATOMIC_FCMPSWAP : FLAT_Real_Atomics_ci <0x3e, FLAT_ATOMIC_FCMPSWAP>;
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|
defm FLAT_ATOMIC_FMIN : FLAT_Real_Atomics_ci <0x3f, FLAT_ATOMIC_FMIN>;
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|
defm FLAT_ATOMIC_FMAX : FLAT_Real_Atomics_ci <0x40, FLAT_ATOMIC_FMAX>;
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defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Real_Atomics_ci <0x5e, FLAT_ATOMIC_FCMPSWAP_X2>;
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|
defm FLAT_ATOMIC_FMIN_X2 : FLAT_Real_Atomics_ci <0x5f, FLAT_ATOMIC_FMIN_X2>;
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|
defm FLAT_ATOMIC_FMAX_X2 : FLAT_Real_Atomics_ci <0x60, FLAT_ATOMIC_FMAX_X2>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// VI
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps> :
|
|
FLAT_Real <op, ps>,
|
|
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
|
|
let AssemblerPredicate = isVI;
|
|
let DecoderNamespace="VI";
|
|
}
|
|
|
|
def FLAT_LOAD_UBYTE_vi : FLAT_Real_vi <0x10, FLAT_LOAD_UBYTE>;
|
|
def FLAT_LOAD_SBYTE_vi : FLAT_Real_vi <0x11, FLAT_LOAD_SBYTE>;
|
|
def FLAT_LOAD_USHORT_vi : FLAT_Real_vi <0x12, FLAT_LOAD_USHORT>;
|
|
def FLAT_LOAD_SSHORT_vi : FLAT_Real_vi <0x13, FLAT_LOAD_SSHORT>;
|
|
def FLAT_LOAD_DWORD_vi : FLAT_Real_vi <0x14, FLAT_LOAD_DWORD>;
|
|
def FLAT_LOAD_DWORDX2_vi : FLAT_Real_vi <0x15, FLAT_LOAD_DWORDX2>;
|
|
def FLAT_LOAD_DWORDX4_vi : FLAT_Real_vi <0x17, FLAT_LOAD_DWORDX4>;
|
|
def FLAT_LOAD_DWORDX3_vi : FLAT_Real_vi <0x16, FLAT_LOAD_DWORDX3>;
|
|
|
|
def FLAT_STORE_BYTE_vi : FLAT_Real_vi <0x18, FLAT_STORE_BYTE>;
|
|
def FLAT_STORE_SHORT_vi : FLAT_Real_vi <0x1a, FLAT_STORE_SHORT>;
|
|
def FLAT_STORE_DWORD_vi : FLAT_Real_vi <0x1c, FLAT_STORE_DWORD>;
|
|
def FLAT_STORE_DWORDX2_vi : FLAT_Real_vi <0x1d, FLAT_STORE_DWORDX2>;
|
|
def FLAT_STORE_DWORDX4_vi : FLAT_Real_vi <0x1f, FLAT_STORE_DWORDX4>;
|
|
def FLAT_STORE_DWORDX3_vi : FLAT_Real_vi <0x1e, FLAT_STORE_DWORDX3>;
|
|
|
|
multiclass FLAT_Real_Atomics_vi <bits<7> op, FLAT_Pseudo ps> {
|
|
def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
|
|
def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
|
|
}
|
|
|
|
defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40, FLAT_ATOMIC_SWAP>;
|
|
defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_vi <0x41, FLAT_ATOMIC_CMPSWAP>;
|
|
defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_vi <0x42, FLAT_ATOMIC_ADD>;
|
|
defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_vi <0x43, FLAT_ATOMIC_SUB>;
|
|
defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_vi <0x44, FLAT_ATOMIC_SMIN>;
|
|
defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_vi <0x45, FLAT_ATOMIC_UMIN>;
|
|
defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_vi <0x46, FLAT_ATOMIC_SMAX>;
|
|
defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_vi <0x47, FLAT_ATOMIC_UMAX>;
|
|
defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_vi <0x48, FLAT_ATOMIC_AND>;
|
|
defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_vi <0x49, FLAT_ATOMIC_OR>;
|
|
defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_vi <0x4a, FLAT_ATOMIC_XOR>;
|
|
defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_vi <0x4b, FLAT_ATOMIC_INC>;
|
|
defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_vi <0x4c, FLAT_ATOMIC_DEC>;
|
|
defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_vi <0x60, FLAT_ATOMIC_SWAP_X2>;
|
|
defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_vi <0x61, FLAT_ATOMIC_CMPSWAP_X2>;
|
|
defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_vi <0x62, FLAT_ATOMIC_ADD_X2>;
|
|
defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_vi <0x63, FLAT_ATOMIC_SUB_X2>;
|
|
defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_vi <0x64, FLAT_ATOMIC_SMIN_X2>;
|
|
defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_vi <0x65, FLAT_ATOMIC_UMIN_X2>;
|
|
defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_vi <0x66, FLAT_ATOMIC_SMAX_X2>;
|
|
defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_vi <0x67, FLAT_ATOMIC_UMAX_X2>;
|
|
defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_vi <0x68, FLAT_ATOMIC_AND_X2>;
|
|
defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_vi <0x69, FLAT_ATOMIC_OR_X2>;
|
|
defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_vi <0x6a, FLAT_ATOMIC_XOR_X2>;
|
|
defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_vi <0x6b, FLAT_ATOMIC_INC_X2>;
|
|
defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_vi <0x6c, FLAT_ATOMIC_DEC_X2>;
|
|
|