forked from OSchip/llvm-project
204 lines
7.2 KiB
C++
204 lines
7.2 KiB
C++
//===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MipsMachineFunction.h"
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool>
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FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
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cl::desc("Always use $gp as the global base register."));
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MipsFunctionInfo::~MipsFunctionInfo() = default;
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bool MipsFunctionInfo::globalBaseRegSet() const {
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return GlobalBaseReg;
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}
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static const TargetRegisterClass &getGlobalBaseRegClass(MachineFunction &MF) {
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auto &STI = static_cast<const MipsSubtarget &>(MF.getSubtarget());
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auto &TM = static_cast<const MipsTargetMachine &>(MF.getTarget());
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if (STI.inMips16Mode())
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return Mips::CPU16RegsRegClass;
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if (STI.inMicroMipsMode())
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return Mips::GPRMM16RegClass;
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if (TM.getABI().IsN64())
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return Mips::GPR64RegClass;
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return Mips::GPR32RegClass;
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}
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Register MipsFunctionInfo::getGlobalBaseReg(MachineFunction &MF) {
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if (!GlobalBaseReg)
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GlobalBaseReg =
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MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF));
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return GlobalBaseReg;
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}
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Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel(MachineFunction &MF) {
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if (!GlobalBaseReg) {
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getGlobalBaseReg(MF);
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initGlobalBaseReg(MF);
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}
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return GlobalBaseReg;
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}
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void MipsFunctionInfo::initGlobalBaseReg(MachineFunction &MF) {
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if (!GlobalBaseReg)
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return;
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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DebugLoc DL;
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const TargetRegisterClass *RC;
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const MipsABIInfo &ABI =
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static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
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RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
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Register V0 = RegInfo.createVirtualRegister(RC);
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Register V1 = RegInfo.createVirtualRegister(RC);
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if (ABI.IsN64()) {
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MF.getRegInfo().addLiveIn(Mips::T9_64);
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MBB.addLiveIn(Mips::T9_64);
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// daddu $v1, $v0, $t9
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// daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = &MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
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.addReg(Mips::T9_64);
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BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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return;
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}
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if (!MF.getTarget().isPositionIndependent()) {
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// Set global register to __gnu_local_gp.
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//
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// lui $v0, %hi(__gnu_local_gp)
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// addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
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return;
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}
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MF.getRegInfo().addLiveIn(Mips::T9);
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MBB.addLiveIn(Mips::T9);
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if (ABI.IsN32()) {
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// addu $v1, $v0, $t9
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// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = &MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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return;
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}
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assert(ABI.IsO32());
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// For O32 ABI, the following instruction sequence is emitted to initialize
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// the global base register:
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//
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// 0. lui $2, %hi(_gp_disp)
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// 1. addiu $2, $2, %lo(_gp_disp)
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// 2. addu $globalbasereg, $2, $t9
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//
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// We emit only the last instruction here.
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//
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// GNU linker requires that the first two instructions appear at the beginning
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// of a function and no instructions be inserted before or between them.
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// The two instructions are emitted during lowering to MC layer in order to
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// avoid any reordering.
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//
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// Register $2 (Mips::V0) is added to the list of live-in registers to ensure
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// the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
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// reads it.
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MF.getRegInfo().addLiveIn(Mips::V0);
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MBB.addLiveIn(Mips::V0);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
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.addReg(Mips::V0).addReg(Mips::T9);
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}
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void MipsFunctionInfo::createEhDataRegsFI(MachineFunction &MF) {
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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for (int I = 0; I < 4; ++I) {
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const TargetRegisterClass &RC =
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static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
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? Mips::GPR64RegClass
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: Mips::GPR32RegClass;
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EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
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TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false);
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}
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}
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void MipsFunctionInfo::createISRRegFI(MachineFunction &MF) {
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// ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
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// The current implementation only supports Mips32r2+ not Mips64rX. Status
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// is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
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// however Mips32r2+ is the supported architecture.
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const TargetRegisterClass &RC = Mips::GPR32RegClass;
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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for (int I = 0; I < 2; ++I)
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ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
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TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false);
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}
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bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
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return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
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|| FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
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}
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bool MipsFunctionInfo::isISRRegFI(int FI) const {
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return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
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}
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MachinePointerInfo MipsFunctionInfo::callPtrInfo(MachineFunction &MF,
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const char *ES) {
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return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES));
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}
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MachinePointerInfo MipsFunctionInfo::callPtrInfo(MachineFunction &MF,
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const GlobalValue *GV) {
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return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV));
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}
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int MipsFunctionInfo::getMoveF64ViaSpillFI(MachineFunction &MF,
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const TargetRegisterClass *RC) {
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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if (MoveF64ViaSpillFI == -1) {
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MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
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TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false);
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}
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return MoveF64ViaSpillFI;
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}
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void MipsFunctionInfo::anchor() {}
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