forked from OSchip/llvm-project
f6302441f0
bool %test(int %X) {
%Y = and int %X, 8
%Z = setne int %Y, 0
ret bool %Z
}
we now generate this:
rlwinm r2, r3, 0, 28, 28
srwi r3, r2, 3
instead of this:
rlwinm r2, r3, 0, 28, 28
srwi r2, r2, 3
rlwinm r3, r2, 0, 31, 31
I'll leave it to Nate to get it down to one instruction. :)
---------------------------------------------------------------------
llvm-svn: 21391
|
||
|---|---|---|
| .. | ||
| SelectionDAG | ||
| AsmPrinter.cpp | ||
| BranchFolding.cpp | ||
| IntrinsicLowering.cpp | ||
| LiveInterval.cpp | ||
| LiveInterval.h | ||
| LiveIntervalAnalysis.cpp | ||
| LiveIntervalAnalysis.h | ||
| LiveVariables.cpp | ||
| MachineBasicBlock.cpp | ||
| MachineCodeEmitter.cpp | ||
| MachineFunction.cpp | ||
| MachineInstr.cpp | ||
| Makefile | ||
| PHIElimination.cpp | ||
| Passes.cpp | ||
| PhysRegTracker.h | ||
| PrologEpilogInserter.cpp | ||
| RegAllocIterativeScan.cpp | ||
| RegAllocLinearScan.cpp | ||
| RegAllocLocal.cpp | ||
| RegAllocSimple.cpp | ||
| TwoAddressInstructionPass.cpp | ||
| UnreachableBlockElim.cpp | ||
| ValueTypes.cpp | ||
| VirtRegMap.cpp | ||
| VirtRegMap.h | ||