llvm-project/llvm/test/CodeGen/Thumb
Matthias Braun 537d039104 RegScavenging: Add scavengeRegisterBackwards()
Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse
to place spills as the very first instruciton of a basic block and thus
artifically increase pressure (test in
test/CodeGen/PowerPC/scavenging.mir:spill_at_begin)

This is a variant of scavengeRegister() that works for
enterBasicBlockEnd()/backward(). The benefit of the backward mode is
that it is not affected by incomplete kill flags.

This patch also changes
PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register
scavenger in backwards mode.

Differential Revision: http://reviews.llvm.org/D21885

llvm-svn: 305625
2017-06-17 02:08:18 +00:00
..
2007-01-31-RegInfoAssert.ll
2007-02-02-JoinIntervalsCrash.ll
2007-05-05-InvalidPushPop.ll
2009-06-18-ThumbCommuteMul.ll
2009-07-20-TwoAddrBug.ll
2009-07-27-PEIAssert.ll
2009-08-12-ConstIslandAssert.ll
2009-08-12-RegInfoAssert.ll
2009-08-20-ISelBug.ll
2009-12-17-pre-regalloc-taildup.ll
2010-06-18-SibCallCrash.ll
2010-07-01-FuncAlign.ll
2010-07-15-debugOrdering.ll In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. 2017-03-14 00:34:14 +00:00
2011-05-11-DAGLegalizer.ll
2011-06-16-NoGPRs.ll
2011-EpilogueBug.ll
2012-04-26-M0ISelBug.ll
2014-06-10-thumb1-ldst-opt-bug.ll
DbgValueOtherTargets.test
PR17309.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
and_neg.ll Add a regression test for PR28348. 2016-06-29 17:34:31 +00:00
asmprinter-bug.ll
barrier.ll ARM: stop emitting blx instructions for most calls on MachO. 2016-05-10 19:17:47 +00:00
bic_imm.ll [Thumb] Reapply r272251 with a fix for PR28348 (mk 2) 2016-07-05 12:37:13 +00:00
callee_save.ll Re-land "[Thumb] Save/restore high registers in Thumb1 pro/epilogues" 2016-10-11 21:14:03 +00:00
cmp-add-fold.ll In Thumb1 mode, the custom lowering for ARMISD::CMPZ could never emit tADDi3 2017-02-17 18:59:16 +00:00
cmp-fold.ll [Thumb1] Teach optimizeCompareInstr about thumb1 compares 2016-09-09 09:51:06 +00:00
constants.ll [Thumb] Fix off-by-one error in r272007 2016-06-14 13:33:07 +00:00
copy_thumb.ll In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. 2017-03-07 09:38:16 +00:00
cortex-m0-unaligned-access.ll
dyn-stackalloc.ll
fastcc.ll
fpconv.ll
fpow.ll
frame_thumb.ll
iabs.ll
inlineasm-imm-thumb.ll
inlineasm-thumb.ll
ispositive.ll [ARM] t2_so_imm_neg had a subtle bug in the conversion, and could trigger UB by negating (int)-2147483648. By pure luck, none of the pre-existing tests triggered this; so I'm adding one. 2017-03-22 15:09:30 +00:00
large-stack.ll RegScavenging: Add scavengeRegisterBackwards() 2017-06-17 02:08:18 +00:00
ldm-merge-call.ll
ldm-merge-struct.ll
ldm-stm-base-materialization-thumb2.ll
ldm-stm-base-materialization.ll
ldm-stm-postinc.ll [Thumb-1] Select post-increment load and store where possible 2016-07-15 08:03:56 +00:00
ldr_ext.ll
ldr_frame.ll
lit.local.cfg
long-setcc.ll
long.ll [Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing `Uses = [CPSR]` 2017-04-21 07:35:21 +00:00
long_shift.ll
machine-cse-physreg.mir Move machine-cse-physreg.mir to test/CodeGen/Thumb 2017-05-24 17:20:47 +00:00
mature-mc-support.ll [LLC] Add an inline assembly diagnostics handler. 2017-02-03 11:14:39 +00:00
mul.ll
optionaldef-scheduling.ll [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs 2017-04-23 06:58:08 +00:00
pop.ll
push.ll [ARM] Generate consistent frame records for Thumb2 2016-08-23 09:19:22 +00:00
remove-unneeded-push-pop.ll [ARM] Fix constant islands pass. 2017-02-22 09:06:21 +00:00
rev.ll
segmented-stacks-dynamic.ll
segmented-stacks.ll
select.ll
sjljehprepare-lower-vector.ll
stack-access.ll Elide stores which are overwritten without being observed. 2017-05-16 19:43:56 +00:00
stack-coloring-without-frame-ptr.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
stack-frame.ll
stack_guard_remat.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
stm-deprecated.ll [ARM] Don't generate deprecated T1 STM. 2017-02-28 23:32:55 +00:00
stm-merge.ll
tbb-reuse.mir [Thumb-1] TBB generation: spot redefinitions of index register 2017-02-13 14:07:39 +00:00
thumb-imm.ll
thumb-ldm.ll
thumb-shrink-wrapping.ll In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. 2017-03-07 09:38:16 +00:00
trap.ll
triple.ll
tst_teq.ll
unord.ll
vargs.ll