forked from OSchip/llvm-project
9790e39f45
For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC,
get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs.
For MIPS, only the DSP ASE has a carry flag, so in the general case it is not
useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes.
Also improve the generation code in such cases for targets with
TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the
comparison node rather than using it in selects. Similarly for ISD::SUBE /
ISD::SUBC.
Address optimization breakage by moving the generation of MIPS specific integer
multiply-accumulate nodes to before legalization.
This revolves PR32713 and PR33424.
Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue!
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D33494
llvm-svn: 305389
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| .. | ||
| add.ll | ||
| addrspacecast.ll | ||
| and.ll | ||
| ashr.ll | ||
| atomicrmx.ll | ||
| call.ll | ||
| extractelement.ll | ||
| indirectbr.ll | ||
| lh_lhu.ll | ||
| load-atomic.ll | ||
| lshr.ll | ||
| mul.ll | ||
| not.ll | ||
| or.ll | ||
| ret.ll | ||
| sdiv.ll | ||
| select-dbl.ll | ||
| select-flt.ll | ||
| select-int.ll | ||
| shl.ll | ||
| sqrt.ll | ||
| srem.ll | ||
| store-atomic.ll | ||
| sub.ll | ||
| udiv.ll | ||
| urem.ll | ||
| xor.ll | ||