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AArch64
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[AArch64] add tests for poor vector intrinsic lowering via legalization (PR38527); NFC
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2018-08-15 17:06:21 +00:00 |
AMDGPU
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AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16
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2018-08-15 21:25:20 +00:00 |
ARC
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ARM
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Revert "[ARM] Allow signed icmps in ARMCodeGenPrepare"
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2018-08-15 20:09:35 +00:00 |
AVR
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…
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BPF
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bpf: add missing RegState to notify MachineInstr verifier necessary register usage
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2018-07-27 16:58:52 +00:00 |
Generic
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[DWARF] Unclamp line table version on Darwin for v5 and later.
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2018-08-08 21:16:50 +00:00 |
Hexagon
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[Hexagon] Map ISD::TRAP to J2_trap0(#0)
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2018-08-09 18:03:45 +00:00 |
Inputs
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Lanai
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…
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MIR
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[DebugInfo][X86] Add start-after flags to MIR tests
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2018-07-12 14:36:48 +00:00 |
MSP430
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…
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Mips
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[mips] Handle branch expansion corner cases
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2018-08-07 10:45:45 +00:00 |
NVPTX
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DAG: Check no-signed-zeros instead of unsafe-fp-math
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2018-08-12 19:09:12 +00:00 |
Nios2
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…
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PowerPC
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[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
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2018-08-15 15:30:36 +00:00 |
RISCV
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[RISCV] Fixed test case failure due to r338047
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2018-07-31 00:36:28 +00:00 |
SPARC
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Revert "[Sparc] Add support for the cycle counter available in GR740"
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2018-08-13 14:18:09 +00:00 |
SystemZ
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[RegisterCoalescer] Ensure that both registers have subranges if one does
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2018-08-15 17:04:58 +00:00 |
Thumb
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[ARM] Adjust AND immediates to make them cheaper to select.
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2018-08-10 21:21:53 +00:00 |
Thumb2
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[ARM] Treat cmn immediates as legal in isLegalICmpImmediate.
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2018-07-10 23:44:37 +00:00 |
WebAssembly
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[WebAssembly] SIMD replace_lane
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2018-08-15 16:18:51 +00:00 |
WinCFGuard
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Rename the cfguard module flag to cfguardtable
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2018-08-10 09:48:53 +00:00 |
WinEH
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…
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X86
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[X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation
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2018-08-15 21:21:52 +00:00 |
XCore
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[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
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2018-07-15 16:27:07 +00:00 |