forked from OSchip/llvm-project
245 lines
10 KiB
LLVM
245 lines
10 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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; GCN-LABEL: {{^}}vgpr:
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; GCN: v_mov_b32_e32 v1, v0
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; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
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; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1
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; GCN: s_waitcnt expcnt(0)
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; GCN-NOT: s_endpgm
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define amdgpu_vs {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
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%x = fadd float %3, 1.0
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%a = insertvalue {float, float} undef, float %x, 0
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%b = insertvalue {float, float} %a, float %3, 1
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ret {float, float} %b
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}
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; GCN-LABEL: {{^}}vgpr_literal:
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; GCN: v_mov_b32_e32 v4, v0
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; GCN: exp 15, 0, 1, 1, 1, v4, v4, v4, v4
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; GCN-DAG: v_mov_b32_e32 v0, 1.0
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; GCN-DAG: v_mov_b32_e32 v1, 2.0
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; GCN-DAG: v_mov_b32_e32 v2, 4.0
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; GCN-DAG: v_mov_b32_e32 v3, -1.0
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; GCN: s_waitcnt expcnt(0)
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; GCN-NOT: s_endpgm
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define amdgpu_vs {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
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ret {float, float, float, float} {float 1.0, float 2.0, float 4.0, float -1.0}
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}
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; GCN: .long 165580
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; GCN-NEXT: .long 562
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; GCN-NEXT: .long 165584
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; GCN-NEXT: .long 562
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; GCN-LABEL: {{^}}vgpr_ps_addr0:
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; GCN-NOT: v_mov_b32_e32 v0
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; GCN-NOT: v_mov_b32_e32 v1
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; GCN-NOT: v_mov_b32_e32 v2
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; GCN: v_mov_b32_e32 v3, v4
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; GCN: v_mov_b32_e32 v4, v6
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; GCN-NOT: s_endpgm
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attributes #0 = { "InitialPSInputAddr"="0" }
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define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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%i0 = extractelement <2 x i32> %4, i32 0
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%i1 = extractelement <2 x i32> %4, i32 1
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%i2 = extractelement <2 x i32> %7, i32 0
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%i3 = extractelement <2 x i32> %8, i32 0
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%f0 = bitcast i32 %i0 to float
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%f1 = bitcast i32 %i1 to float
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%f2 = bitcast i32 %i2 to float
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%f3 = bitcast i32 %i3 to float
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%r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
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%r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
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%r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
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%r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
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%r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
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ret {float, float, float, float, float} %r4
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}
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; GCN: .long 165580
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; GCN-NEXT: .long 1
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; GCN-NEXT: .long 165584
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; GCN-NEXT: .long 1
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; GCN-LABEL: {{^}}ps_input_ena_no_inputs:
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; GCN: v_mov_b32_e32 v0, 1.0
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; GCN-NOT: s_endpgm
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define amdgpu_ps float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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ret float 1.0
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}
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; GCN: .long 165580
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; GCN-NEXT: .long 2081
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; GCN-NEXT: .long 165584
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; GCN-NEXT: .long 2081
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; GCN-LABEL: {{^}}ps_input_ena_pos_w:
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; GCN-DAG: v_mov_b32_e32 v0, v4
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; GCN-DAG: v_mov_b32_e32 v1, v2
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; GCN: v_mov_b32_e32 v2, v3
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; GCN-NOT: s_endpgm
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define amdgpu_ps {float, <2 x float>} @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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%f = bitcast <2 x i32> %8 to <2 x float>
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%s = insertvalue {float, <2 x float>} undef, float %14, 0
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%s1 = insertvalue {float, <2 x float>} %s, <2 x float> %f, 1
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ret {float, <2 x float>} %s1
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}
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; GCN: .long 165580
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; GCN-NEXT: .long 562
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; GCN-NEXT: .long 165584
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; GCN-NEXT: .long 563
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; GCN-LABEL: {{^}}vgpr_ps_addr1:
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; GCN-DAG: v_mov_b32_e32 v0, v2
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; GCN-DAG: v_mov_b32_e32 v1, v3
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; GCN: v_mov_b32_e32 v2, v4
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; GCN-DAG: v_mov_b32_e32 v3, v6
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; GCN-DAG: v_mov_b32_e32 v4, v8
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; GCN-NOT: s_endpgm
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attributes #1 = { "InitialPSInputAddr"="1" }
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define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr1([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 {
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%i0 = extractelement <2 x i32> %4, i32 0
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%i1 = extractelement <2 x i32> %4, i32 1
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%i2 = extractelement <2 x i32> %7, i32 0
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%i3 = extractelement <2 x i32> %8, i32 0
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%f0 = bitcast i32 %i0 to float
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%f1 = bitcast i32 %i1 to float
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%f2 = bitcast i32 %i2 to float
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%f3 = bitcast i32 %i3 to float
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%r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
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%r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
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%r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
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%r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
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%r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
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ret {float, float, float, float, float} %r4
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}
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; GCN: .long 165580
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; GCN-NEXT: .long 562
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; GCN-NEXT: .long 165584
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; GCN-NEXT: .long 631
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; GCN-LABEL: {{^}}vgpr_ps_addr119:
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; GCN-DAG: v_mov_b32_e32 v0, v2
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; GCN-DAG: v_mov_b32_e32 v1, v3
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; GCN: v_mov_b32_e32 v2, v6
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; GCN: v_mov_b32_e32 v3, v8
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; GCN: v_mov_b32_e32 v4, v12
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; GCN-NOT: s_endpgm
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attributes #2 = { "InitialPSInputAddr"="119" }
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define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr119([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #2 {
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%i0 = extractelement <2 x i32> %4, i32 0
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%i1 = extractelement <2 x i32> %4, i32 1
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%i2 = extractelement <2 x i32> %7, i32 0
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%i3 = extractelement <2 x i32> %8, i32 0
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%f0 = bitcast i32 %i0 to float
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%f1 = bitcast i32 %i1 to float
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%f2 = bitcast i32 %i2 to float
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%f3 = bitcast i32 %i3 to float
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%r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
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%r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
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%r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
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%r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
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%r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
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ret {float, float, float, float, float} %r4
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}
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; GCN: .long 165580
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; GCN-NEXT: .long 562
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; GCN-NEXT: .long 165584
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; GCN-NEXT: .long 946
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; GCN-LABEL: {{^}}vgpr_ps_addr418:
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; GCN-NOT: v_mov_b32_e32 v0
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; GCN-NOT: v_mov_b32_e32 v1
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; GCN-NOT: v_mov_b32_e32 v2
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; GCN: v_mov_b32_e32 v3, v4
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; GCN: v_mov_b32_e32 v4, v8
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; GCN-NOT: s_endpgm
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attributes #3 = { "InitialPSInputAddr"="418" }
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define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr418([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #3 {
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%i0 = extractelement <2 x i32> %4, i32 0
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%i1 = extractelement <2 x i32> %4, i32 1
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%i2 = extractelement <2 x i32> %7, i32 0
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%i3 = extractelement <2 x i32> %8, i32 0
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%f0 = bitcast i32 %i0 to float
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%f1 = bitcast i32 %i1 to float
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%f2 = bitcast i32 %i2 to float
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%f3 = bitcast i32 %i3 to float
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%r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
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%r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
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%r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
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%r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
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%r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
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ret {float, float, float, float, float} %r4
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}
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; GCN-LABEL: {{^}}sgpr:
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; GCN: s_add_i32 s0, s3, 2
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; GCN: s_mov_b32 s2, s3
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; GCN-NOT: s_endpgm
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define amdgpu_vs {i32, i32, i32} @sgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
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%x = add i32 %2, 2
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%a = insertvalue {i32, i32, i32} undef, i32 %x, 0
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%b = insertvalue {i32, i32, i32} %a, i32 %1, 1
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%c = insertvalue {i32, i32, i32} %a, i32 %2, 2
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ret {i32, i32, i32} %c
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}
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; GCN-LABEL: {{^}}sgpr_literal:
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; GCN: s_mov_b32 s0, 5
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; GCN-NOT: s_mov_b32 s0, s0
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; GCN-DAG: s_mov_b32 s1, 6
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; GCN-DAG: s_mov_b32 s2, 7
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; GCN-DAG: s_mov_b32 s3, 8
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; GCN-NOT: s_endpgm
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define amdgpu_vs {i32, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
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%x = add i32 %2, 2
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ret {i32, i32, i32, i32} {i32 5, i32 6, i32 7, i32 8}
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}
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; GCN-LABEL: {{^}}both:
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; GCN: v_mov_b32_e32 v1, v0
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; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1
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; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
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; GCN-DAG: s_add_i32 s0, s3, 2
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; GCN-DAG: s_mov_b32 s1, s2
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; GCN: s_mov_b32 s2, s3
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; GCN: s_waitcnt expcnt(0)
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; GCN-NOT: s_endpgm
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define amdgpu_vs {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
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%v = fadd float %3, 1.0
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%s = add i32 %2, 2
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%a0 = insertvalue {float, i32, float, i32, i32} undef, float %v, 0
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%a1 = insertvalue {float, i32, float, i32, i32} %a0, i32 %s, 1
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%a2 = insertvalue {float, i32, float, i32, i32} %a1, float %3, 2
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%a3 = insertvalue {float, i32, float, i32, i32} %a2, i32 %1, 3
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%a4 = insertvalue {float, i32, float, i32, i32} %a3, i32 %2, 4
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ret {float, i32, float, i32, i32} %a4
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}
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; GCN-LABEL: {{^}}structure_literal:
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; GCN: v_mov_b32_e32 v3, v0
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; GCN: exp 15, 0, 1, 1, 1, v3, v3, v3, v3
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; GCN-DAG: v_mov_b32_e32 v0, 1.0
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; GCN-DAG: s_mov_b32 s0, 2
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; GCN-DAG: s_mov_b32 s1, 3
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; GCN-DAG: v_mov_b32_e32 v1, 2.0
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; GCN-DAG: v_mov_b32_e32 v2, 4.0
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; GCN: s_waitcnt expcnt(0)
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define amdgpu_vs {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
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ret {{float, i32}, {i32, <2 x float>}} {{float, i32} {float 1.0, i32 2}, {i32, <2 x float>} {i32 3, <2 x float> <float 2.0, float 4.0>}}
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}
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