llvm-project/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir

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# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
# Check that %11 and %20 have been coalesced.
# CHECK: IMAGE_SAMPLE_C_D_O_V1_V16 %[[REG:[0-9]+]]
# CHECK: IMAGE_SAMPLE_C_D_O_V1_V16 %[[REG]]
---
name: main
alignment: 0
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_64 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_256 }
- { id: 4, class: sreg_128 }
- { id: 5, class: sreg_256 }
- { id: 6, class: sreg_128 }
- { id: 7, class: sreg_512 }
- { id: 9, class: vreg_512 }
- { id: 11, class: vreg_512 }
- { id: 18, class: vgpr_32 }
- { id: 20, class: vreg_512 }
- { id: 27, class: vgpr_32 }
liveins:
- { reg: '%sgpr2_sgpr3', virtual-reg: '%0' }
- { reg: '%vgpr2', virtual-reg: '%1' }
- { reg: '%vgpr3', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0:
liveins: %sgpr2_sgpr3, %vgpr2, %vgpr3
%0 = COPY %sgpr2_sgpr3
%1 = COPY %vgpr2
%2 = COPY %vgpr3
%3 = S_LOAD_DWORDX8_IMM %0, 0
%4 = S_LOAD_DWORDX4_IMM %0, 12
%5 = S_LOAD_DWORDX8_IMM %0, 16
%6 = S_LOAD_DWORDX4_IMM %0, 28
undef %7.sub0 = S_MOV_B32 212739
%20 = COPY %7
%11 = COPY %20
%11.sub1 = COPY %1
%11.sub2 = COPY %1
%11.sub3 = COPY %1
%11.sub4 = COPY %1
%11.sub5 = COPY %1
%11.sub6 = COPY %1
%11.sub7 = COPY %1
%11.sub8 = COPY %1
dead %18 = IMAGE_SAMPLE_C_D_O_V1_V16 %11, %3, %4, 1, 0, 0, 0, 0, 0, 0, -1, implicit %exec
%20.sub1 = COPY %2
%20.sub2 = COPY %2
%20.sub3 = COPY %2
%20.sub4 = COPY %2
%20.sub5 = COPY %2
%20.sub6 = COPY %2
%20.sub7 = COPY %2
%20.sub8 = COPY %2
dead %27 = IMAGE_SAMPLE_C_D_O_V1_V16 %20, %5, %6, 1, 0, 0, 0, 0, 0, 0, -1, implicit %exec
...