forked from OSchip/llvm-project
46 lines
2.1 KiB
LLVM
46 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.8.0"
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define i32 @foo(i32* nocapture %A, i32 %n) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CALL:%.*]] = tail call i32 (...) @bar()
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[N:%.*]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[N]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[N]], i32 2
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[N]], i32 3
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; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <4 x i32> [[TMP3]], <i32 5, i32 9, i32 3, i32 10>
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; CHECK-NEXT: [[TMP5:%.*]] = shl <4 x i32> [[TMP3]], <i32 5, i32 9, i32 3, i32 10>
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; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
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; CHECK-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[TMP6]], <i32 9, i32 9, i32 9, i32 9>
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; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32* [[A:%.*]] to <4 x i32>*
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; CHECK-NEXT: store <4 x i32> [[TMP7]], <4 x i32>* [[TMP8]], align 4
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; CHECK-NEXT: ret i32 undef
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;
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entry:
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%call = tail call i32 (...) @bar() #2
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%mul = mul nsw i32 %n, 5
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%add = add nsw i32 %mul, 9
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store i32 %add, i32* %A, align 4
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%mul1 = mul nsw i32 %n, 9
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%add2 = add nsw i32 %mul1, 9
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%arrayidx3 = getelementptr inbounds i32, i32* %A, i64 1
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store i32 %add2, i32* %arrayidx3, align 4
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%mul4 = shl i32 %n, 3
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%add5 = add nsw i32 %mul4, 9
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%arrayidx6 = getelementptr inbounds i32, i32* %A, i64 2
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store i32 %add5, i32* %arrayidx6, align 4
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%mul7 = mul nsw i32 %n, 10
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%add8 = add nsw i32 %mul7, 9
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%arrayidx9 = getelementptr inbounds i32, i32* %A, i64 3
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store i32 %add8, i32* %arrayidx9, align 4
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ret i32 undef
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}
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; We can still vectorize the stores below.
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declare i32 @bar(...)
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