..
AsmParser
[MC] De-capitalize another set of MCStreamer::Emit* functions
2020-02-14 19:26:52 -08:00
Disassembler
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
MCTargetDesc
[NFC][RISCV] Fixing typo in comment.
2020-02-05 11:30:11 -08:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[RISCV] Support ABI checking with per function target-features
2020-01-22 08:12:28 -08:00
CMakeLists.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
LLVMBuild.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.td
[TableGen] Support combining AssemblerPredicates with ORs
2020-03-13 17:13:51 +00:00
RISCVAsmPrinter.cpp
[RISCV] Compress instructions based on function features
2020-02-28 11:52:55 +00:00
RISCVCallLowering.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVCallLowering.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVCallingConv.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVExpandPseudoInsts.cpp
[RISCV] Use addi rather than add x0
2019-11-14 18:43:38 +00:00
RISCVFrameLowering.cpp
[Alignment][NFC] Deprecate getMaxAlignment
2020-03-18 14:48:45 +01:00
RISCVFrameLowering.h
ArrayRef'ize restoreCalleeSavedRegisters. NFCI.
2020-02-29 09:50:23 +01:00
RISCVISelDAGToDAG.cpp
[SelectionDAG] Disallow indirect "i" constraint
2019-12-29 16:50:42 -08:00
RISCVISelLowering.cpp
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
RISCVISelLowering.h
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
RISCVInstrFormats.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrFormatsC.td
…
RISCVInstrInfo.cpp
[NFC] unsigned->Register in storeRegTo/loadRegFromStack
2020-02-03 14:22:16 +01:00
RISCVInstrInfo.h
[NFC] unsigned->Register in storeRegTo/loadRegFromStack
2020-02-03 14:22:16 +01:00
RISCVInstrInfo.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVInstrInfoA.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoC.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
RISCVInstrInfoF.td
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
RISCVInstrInfoM.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstructionSelector.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVMCInstLower.cpp
…
RISCVMachineFunctionInfo.h
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
RISCVMergeBaseOffset.cpp
[RISCV] Convert registers from unsigned to Register
2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
2020-03-18 19:52:23 +00:00
RISCVRegisterBankInfo.h
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
2020-03-18 19:52:23 +00:00
RISCVRegisterBanks.td
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp
[RISCV] Correct the CallPreservedMask for the function call in an interrupt handler
2020-02-15 09:14:04 +08:00
RISCVRegisterInfo.h
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
RISCVRegisterInfo.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVSchedRocket32.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSchedRocket64.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSchedule.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSubtarget.cpp
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
2020-03-18 19:52:23 +00:00
RISCVSubtarget.h
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Check the target-abi module flag matches the option
2020-01-21 07:32:12 -08:00
RISCVTargetMachine.h
[RISCV] Add subtargets initialized with target feature
2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp
Revert "Honor -fuse-init-array when os is not specified on x86"
2019-12-17 07:36:59 -08:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
Rename TTI::getIntImmCost for instructions and intrinsics
2019-12-11 18:00:20 -08:00
RISCVTargetTransformInfo.h
Rename TTI::getIntImmCost for instructions and intrinsics
2019-12-11 18:00:20 -08:00
3c24aee7ee