forked from OSchip/llvm-project
161 lines
6.3 KiB
C++
161 lines
6.3 KiB
C++
//===------------------------- LSUnit.h --------------------------*- C++-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// A Load/Store unit class that models load/store queues and that implements
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/// a simple weak memory consistency model.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_LSUNIT_H
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#define LLVM_TOOLS_LLVM_MCA_LSUNIT_H
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <set>
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#define DEBUG_TYPE "llvm-mca"
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namespace mca {
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/// \brief A Load/Store Unit implementing a load and store queues.
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///
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/// This class implements a load queue and a store queue to emulate the
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/// out-of-order execution of memory operations.
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/// Each load (or store) consumes an entry in the load (or store) queue.
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///
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/// Rules are:
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/// 1) A younger load is allowed to pass an older load only if there are no
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/// stores nor barriers in between the two loads.
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/// 2) An younger store is not allowed to pass an older store.
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/// 3) A younger store is not allowed to pass an older load.
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/// 4) A younger load is allowed to pass an older store only if the load does
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/// not alias with the store.
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///
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/// This class optimistically assumes that loads don't alias store operations.
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/// Under this assumption, younger loads are always allowed to pass older
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/// stores (this would only affects rule 4).
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/// Essentially, this LSUnit doesn't attempt to run any sort alias analysis to
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/// predict when loads and stores don't alias with eachother.
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///
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/// To enforce aliasing between loads and stores, flag `AssumeNoAlias` must be
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/// set to `false` by the constructor of LSUnit.
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///
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/// In the case of write-combining memory, rule 2. could be relaxed to allow
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/// reordering of non-aliasing store operations. At the moment, this is not
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/// allowed.
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/// To put it in another way, there is no option to specify a different memory
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/// type for memory operations (example: write-through, write-combining, etc.).
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/// Also, there is no way to weaken the memory model, and this unit currently
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/// doesn't support write-combining behavior.
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///
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/// No assumptions are made on the size of the store buffer.
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/// As mentioned before, this class doesn't perform alias analysis.
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/// Consequently, LSUnit doesn't know how to identify cases where
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/// store-to-load forwarding may occur.
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///
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/// LSUnit doesn't attempt to predict whether a load or store hits or misses
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/// the L1 cache. To be more specific, LSUnit doesn't know anything about
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/// the cache hierarchy and memory types.
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/// It only knows if an instruction "mayLoad" and/or "mayStore". For loads, the
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/// scheduling model provides an "optimistic" load-to-use latency (which usually
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/// matches the load-to-use latency for when there is a hit in the L1D).
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///
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/// Class MCInstrDesc in LLVM doesn't know about serializing operations, nor
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/// memory-barrier like instructions.
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/// LSUnit conservatively assumes that an instruction which `mayLoad` and has
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/// `unmodeled side effects` behave like a "soft" load-barrier. That means, it
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/// serializes loads without forcing a flush of the load queue.
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/// Similarly, instructions that both `mayStore` and have `unmodeled side
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/// effects` are treated like store barriers. A full memory
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/// barrier is a 'mayLoad' and 'mayStore' instruction with unmodeled side
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/// effects. This is obviously inaccurate, but this is the best that we can do
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/// at the moment.
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///
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/// Each load/store barrier consumes one entry in the load/store queue. A
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/// load/store barrier enforces ordering of loads/stores:
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/// - A younger load cannot pass a load barrier.
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/// - A younger store cannot pass a store barrier.
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///
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/// A younger load has to wait for the memory load barrier to execute.
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/// A load/store barrier is "executed" when it becomes the oldest entry in
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/// the load/store queue(s). That also means, all the older loads/stores have
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/// already been executed.
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class LSUnit {
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// Load queue size.
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// LQ_Size == 0 means that there are infinite slots in the load queue.
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unsigned LQ_Size;
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// Store queue size.
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// SQ_Size == 0 means that there are infinite slots in the store queue.
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unsigned SQ_Size;
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// If true, loads will never alias with stores. This is the default.
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bool NoAlias;
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std::set<unsigned> LoadQueue;
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std::set<unsigned> StoreQueue;
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void assignLQSlot(unsigned Index);
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void assignSQSlot(unsigned Index);
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bool isReadyNoAlias(unsigned Index) const;
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// An instruction that both 'mayStore' and 'HasUnmodeledSideEffects' is
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// conservatively treated as a store barrier. It forces older store to be
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// executed before newer stores are issued.
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std::set<unsigned> StoreBarriers;
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// An instruction that both 'MayLoad' and 'HasUnmodeledSideEffects' is
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// conservatively treated as a load barrier. It forces older loads to execute
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// before newer loads are issued.
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std::set<unsigned> LoadBarriers;
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public:
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LSUnit(unsigned LQ = 0, unsigned SQ = 0, bool AssumeNoAlias = false)
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: LQ_Size(LQ), SQ_Size(SQ), NoAlias(AssumeNoAlias) {}
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#ifndef NDEBUG
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void dump() const;
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#endif
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bool isSQEmpty() const { return StoreQueue.empty(); }
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bool isLQEmpty() const { return LoadQueue.empty(); }
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bool isSQFull() const { return SQ_Size != 0 && StoreQueue.size() == SQ_Size; }
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bool isLQFull() const { return LQ_Size != 0 && LoadQueue.size() == LQ_Size; }
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void reserve(unsigned Index, bool MayLoad, bool MayStore, bool IsMemBarrier) {
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if (!MayLoad && !MayStore)
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return;
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if (MayLoad) {
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if (IsMemBarrier)
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LoadBarriers.insert(Index);
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assignLQSlot(Index);
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}
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if (MayStore) {
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if (IsMemBarrier)
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StoreBarriers.insert(Index);
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assignSQSlot(Index);
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}
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}
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// The rules are:
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// 1. A store may not pass a previous store.
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// 2. A load may not pass a previous store unless flag 'NoAlias' is set.
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// 3. A load may pass a previous load.
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// 4. A store may not pass a previous load (regardless of flag 'NoAlias').
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// 5. A load has to wait until an older load barrier is fully executed.
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// 6. A store has to wait until an older store barrier is fully executed.
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bool isReady(unsigned Index) const;
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void onInstructionExecuted(unsigned Index);
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};
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} // namespace mca
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#endif
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