forked from OSchip/llvm-project
162 lines
5.2 KiB
LLVM
162 lines
5.2 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; These tests check that floating point comparisons which are used by select
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; to store integer true (-1) and false (0) values are lowered to one of the
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; SET*DX10 instructions.
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; CHECK: {{^}}fcmp_une_select_fptosi:
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; CHECK: LSHR
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; CHECK-NEXT: SETNE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp une float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_une_select_i32:
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; CHECK: LSHR
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; CHECK-NEXT: SETNE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp une float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_oeq_select_fptosi:
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; CHECK: LSHR
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; CHECK-NEXT: SETE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_oeq_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp oeq float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_oeq_select_i32:
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; CHECK: LSHR
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; CHECK-NEXT: SETE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_oeq_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp oeq float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_ogt_select_fptosi:
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; CHECK: LSHR
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; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_ogt_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ogt float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_ogt_select_i32:
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; CHECK: LSHR
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; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_ogt_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ogt float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_oge_select_fptosi:
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; CHECK: LSHR
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; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_oge_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp oge float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_oge_select_i32:
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; CHECK: LSHR
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; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_oge_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp oge float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_ole_select_fptosi:
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; CHECK: LSHR
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; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_ole_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ole float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_ole_select_i32:
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; CHECK: LSHR
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; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_ole_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ole float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_olt_select_fptosi:
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; CHECK: LSHR
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; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_olt_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp olt float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}fcmp_olt_select_i32:
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; CHECK: LSHR
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; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
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; CHECK-NEXT: 1084227584(5.000000e+00)
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define amdgpu_kernel void @fcmp_olt_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp olt float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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