forked from OSchip/llvm-project
218 lines
9.5 KiB
LLVM
218 lines
9.5 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; FIXME: None of these trigger madmk emission anymore. It is still
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; possible, but requires the correct registers to be used which is
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; hard to trigger.
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare float @llvm.fabs.f32(float) nounwind readnone
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; GCN-LABEL: {{^}}madmk_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]]
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define amdgpu_kernel void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load volatile float, float addrspace(1)* %gep.0, align 4
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%b = load volatile float, float addrspace(1)* %gep.1, align 4
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}madmk_2_use_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000
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; GCN-DAG: v_mac_f32_e32 [[VB]], [[SK]], [[VA]]
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; GCN-DAG: v_mac_f32_e32 [[VC]], [[SK]], [[VA]]
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; GCN: s_endpgm
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define amdgpu_kernel void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
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%in.gep.2 = getelementptr float, float addrspace(1)* %in.gep.0, i32 2
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%out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
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%a = load volatile float, float addrspace(1)* %in.gep.0, align 4
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%b = load volatile float, float addrspace(1)* %in.gep.1, align 4
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%c = load volatile float, float addrspace(1)* %in.gep.2, align 4
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%mul0 = fmul float %a, 10.0
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%mul1 = fmul float %a, 10.0
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%madmk0 = fadd float %mul0, %b
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%madmk1 = fadd float %mul1, %c
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store float %madmk0, float addrspace(1)* %out.gep.0, align 4
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store float %madmk1, float addrspace(1)* %out.gep.1, align 4
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ret void
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}
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; We don't get any benefit if the constant is an inline immediate.
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; GCN-LABEL: {{^}}madmk_inline_imm_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]]
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define amdgpu_kernel void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load volatile float, float addrspace(1)* %gep.0, align 4
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%b = load volatile float, float addrspace(1)* %gep.1, align 4
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%mul = fmul float %a, 4.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_s_madmk_f32:
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; GCN-NOT: v_madmk_f32
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; GCN: v_mac_f32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @s_s_madmk_f32(float addrspace(1)* noalias %out, [8 x i32], float %a, [8 x i32], float %b) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_s_madmk_f32:
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; GCN: s_load_dword [[SREG:s[0-9]+]]
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; GCN: buffer_load_dword [[VREG1:v[0-9]+]]
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; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]]
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; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]]
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; GCN: s_endpgm
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define amdgpu_kernel void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep.0, align 4
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}scalar_vector_madmk_f32:
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; GCN-NOT: v_madmk_f32
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; GCN: v_mac_f32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @scalar_vector_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %a) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%b = load float, float addrspace(1)* %gep.0, align 4
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000
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; GCN: v_mad_f32 {{v[0-9]+}}, |[[VA]]|, [[SK]], [[VB]]
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define amdgpu_kernel void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load volatile float, float addrspace(1)* %gep.0, align 4
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%b = load volatile float, float addrspace(1)* %gep.1, align 4
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%a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
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%mul = fmul float %a.fabs, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{[sv][0-9]+}}, |{{v[0-9]+}}|
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define amdgpu_kernel void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load volatile float, float addrspace(1)* %gep.0, align 4
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%b = load volatile float, float addrspace(1)* %gep.1, align 4
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%b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b.fabs
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}madmk_add_inline_imm_f32:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: s_mov_b32 [[SK:s[0-9]+]], 0x41200000
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; GCN: v_mad_f32 {{v[0-9]+}}, [[A]], [[SK]], 2.0
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define amdgpu_kernel void @madmk_add_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep.0, align 4
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, 2.0
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; SI-LABEL: {{^}}kill_madmk_verifier_error:
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; SI: s_xor_b64
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; SI: v_mac_f32_e32 {{v[0-9]+}}, 0x472aee8c, {{v[0-9]+}}
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; SI: s_or_b64
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define amdgpu_kernel void @kill_madmk_verifier_error() nounwind {
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bb:
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br label %bb2
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bb1: ; preds = %bb2
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ret void
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bb2: ; preds = %bb6, %bb
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%tmp = phi float [ undef, %bb ], [ %tmp8, %bb6 ]
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
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%f_tid = bitcast i32 %tid to float
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%tmp3 = fsub float %f_tid, %tmp
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%tmp5 = fcmp oeq float %tmp3, 1.000000e+04
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br i1 %tmp5, label %bb1, label %bb6
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bb6: ; preds = %bb2
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%tmp7 = fmul float %tmp, 0x40E55DD180000000
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%tmp8 = fadd float %tmp7, %tmp
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br label %bb2
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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attributes #1 = { nounwind readnone }
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