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llvm-project/llvm/test/CodeGen
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Craig Topper b2368fbdf4 [SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left. 
This seems to improve X86's ability to match this into an address computation. Otherwise the other operand gets assigned to the base register and the stack pointer + frame index ends up in the index register. But index registers can't encode ESP/RSP so we end up having to move it into another register to meet the constraint.

I could try to improve the address matcher in X86, but swapping the producer seemed easier. Several other places already have the operands in this order so this is at least consistent.

llvm-svn: 321370
 		2017-12-22 17:18:13 +00:00
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AArch64 [SimplifyCFG] Avoid quadratic on a predecessors number behavior in instruction sinking. 2017-12-21 01:22:13 +00:00
AMDGPU [AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed. 2017-12-19 19:26:23 +00:00
ARC
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ARM [ARM GlobalISel] Support G_INTTOPTR and G_PTRTOINT for s32 2017-12-22 13:05:51 +00:00
AVR [AVR] Fix two CodeGen tests 2017-12-09 07:51:43 +00:00
BPF bpf: add support for objdump -print-imm-hex 2017-12-20 19:39:58 +00:00
Generic [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Hexagon [Hexagon] Allow construction of HVX vector predicates 2017-12-20 20:49:43 +00:00
Inputs
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Lanai [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
MIR [YAML] Add support for non-printable characters 2017-12-18 17:38:03 +00:00
MSP430 [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Mips [SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left. 2017-12-22 17:18:13 +00:00
NVPTX [Memcpy Loop Lowering] Remove the fixed int8 lowering. 2017-12-18 15:31:14 +00:00
Nios2 [Nios2] final infrastructure to provide compilation of a return from a function 2017-12-07 12:35:02 +00:00
PowerPC [SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left. 2017-12-22 17:18:13 +00:00
RISCV [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
SPARC Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion 2017-12-11 22:25:04 +00:00
SystemZ [MachineOperand][MIR] Add isRenamable to MachineOperand. 2017-12-12 17:53:59 +00:00
Thumb [ARM] Add tests for D34515 2017-12-15 09:24:46 +00:00
Thumb2 [ARM] Register the Thumb2SizeReducePass. NFC 2017-12-19 12:19:08 +00:00
WebAssembly [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors 2017-12-15 00:17:10 +00:00
WinEH Make x86 __ehhandler comdat if parent function is 2017-10-20 17:04:43 +00:00
X86 [SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left. 2017-12-22 17:18:13 +00:00
XCore
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