forked from OSchip/llvm-project
0e48bd24e2
The family of 'dual-accumulating' vector multiply-add instructions (VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and unsigned integer types, and they all have an 'exchange' variant (with an X in the name) that modifies which pairs of vector lanes in the two inputs are multiplied together. But there's a clause in the spec that says that the X variants //don't// operate on unsigned integer types, only signed. You can have X, or unsigned, or neither, but not both. We didn't notice that clause when we implemented the MC support for these instructions, so LLVM believes that things like VMLADAVX.U8 do exist, contradicting the spec. Here I fix that by conditioning them out in Tablegen. In order to do that, I've reversed the nesting order of the Tablegen multiclasses for those instructions. Previously, the innermost multiclass generated the X and not-X variants, and the one outside that generated the A and not-A variants. Now X is done by the outer multiclass, which allows me to bypass that one when I only want the two not-X variants. Changing the multiclass nesting order also changes the names of the instruction ids unless I make a special effort not to. I decided that while I was changing them anyway I'd make them look nicer; so now the instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32, instead of cumbersome _noacc_noexch suffixes. The corresponding multiply-subtract instructions are unaffected. Those don't accept unsigned types at all, either in the spec or in LLVM. Reviewers: ostannard, dmgreen Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67214 llvm-svn: 371405 |
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| .. | ||
| addrmode2-reencoding.txt | ||
| arm-LDREXD-reencoding.txt | ||
| arm-STREXD-reencoding.txt | ||
| arm-tests.txt | ||
| arm-thumb-trustzone.txt | ||
| arm-trustzone.txt | ||
| arm-vmrs_vmsr.txt | ||
| armv8.1a.txt | ||
| armv8.2a-dotprod-a32.s | ||
| armv8.2a-dotprod-t32.s | ||
| armv8.3a-js-arm.txt | ||
| armv8.3a-js-thumb.txt | ||
| armv8.4a-trace-a32.txt | ||
| armv8.4a-trace-t32.txt | ||
| armv8.5a-sb-thumb.txt | ||
| armv8.5a-sb.txt | ||
| armv8a-fpmul-a32.txt | ||
| armv8a-fpmul-t32.txt | ||
| basic-arm-instructions-v8.txt | ||
| basic-arm-instructions.txt | ||
| clrm.txt | ||
| coprocessors-arm.txt | ||
| coprocessors-thumb.txt | ||
| crc32-thumb.txt | ||
| crc32.txt | ||
| csdb-arm.txt | ||
| csdb-thumb.txt | ||
| d16.txt | ||
| dfb-arm.txt | ||
| dfb-thumb.txt | ||
| fp-armv8.txt | ||
| fp-encoding.txt | ||
| fullfp16-arm-neg.txt | ||
| fullfp16-arm-nopred.txt | ||
| fullfp16-arm.txt | ||
| fullfp16-neon-arm-neg.txt | ||
| fullfp16-neon-arm.txt | ||
| fullfp16-neon-thumb-neg.txt | ||
| fullfp16-neon-thumb.txt | ||
| fullfp16-thumb-neg.txt | ||
| fullfp16-thumb-nopred.txt | ||
| fullfp16-thumb.txt | ||
| hex-immediates.txt | ||
| invalid-FSTMX-arm.txt | ||
| invalid-IT-CC15.txt | ||
| invalid-armv7.txt | ||
| invalid-armv8.1a.txt | ||
| invalid-armv8.txt | ||
| invalid-because-armv7.txt | ||
| invalid-thumb-MSR-MClass.txt | ||
| invalid-thumbv7-xfail.txt | ||
| invalid-thumbv7.txt | ||
| invalid-thumbv8.1a.txt | ||
| invalid-thumbv8.txt | ||
| invalid-virtexts.arm.txt | ||
| ldrd-armv4.txt | ||
| lit.local.cfg | ||
| load-store-acquire-release-v8-thumb.txt | ||
| load-store-acquire-release-v8.txt | ||
| marked-up-thumb.txt | ||
| memory-arm-instructions.txt | ||
| move-banked-regs-arm.txt | ||
| move-banked-regs-thumb.txt | ||
| mve-bitops.txt | ||
| mve-float.txt | ||
| mve-integer.txt | ||
| mve-interleave.txt | ||
| mve-load-store.txt | ||
| mve-minmax.txt | ||
| mve-misc.txt | ||
| mve-qdest-qsrc.txt | ||
| mve-qdest-rsrc.txt | ||
| mve-reductions.txt | ||
| mve-scalar-shift-unpredictable.txt | ||
| mve-scalar-shift.txt | ||
| mve-shifts.txt | ||
| mve-vcmp.txt | ||
| mve-vmov-lane.txt | ||
| mve-vmov-pair.txt | ||
| mve-vpt.txt | ||
| neon-complex-arm.txt | ||
| neon-complex-thumb.txt | ||
| neon-crypto.txt | ||
| neon-tests.txt | ||
| neon-v8.txt | ||
| neon.txt | ||
| neont-VLD-reencoding.txt | ||
| neont-VST-reencoding.txt | ||
| neont2.txt | ||
| ras-extension-arm.txt | ||
| ras-extension-thumb.txt | ||
| thumb-MSR-MClass.txt | ||
| thumb-fp-armv8.txt | ||
| thumb-neon-crypto.txt | ||
| thumb-neon-v8.txt | ||
| thumb-printf.txt | ||
| thumb-tests.txt | ||
| thumb-v8.1a.txt | ||
| thumb-v8.txt | ||
| thumb-vmrs_vmsr.txt | ||
| thumb1.txt | ||
| thumb2-bit-15.txt | ||
| thumb2-preloads.txt | ||
| thumb2-v8.1m.txt | ||
| thumb2-v8.txt | ||
| thumb2-v8m.txt | ||
| thumb2.txt | ||
| thumbv8.1m-vmrs-vmsr.txt | ||
| thumbv8.1m.s | ||
| unpredictable-ADC-arm.txt | ||
| unpredictable-ADDREXT3-arm.txt | ||
| unpredictable-AExtI-arm.txt | ||
| unpredictable-AI1cmp-arm.txt | ||
| unpredictable-BFI.txt | ||
| unpredictable-LDR-arm.txt | ||
| unpredictable-LDRD-arm.txt | ||
| unpredictable-LSL-regform.txt | ||
| unpredictable-MRRC2-arm.txt | ||
| unpredictable-MRS-arm.txt | ||
| unpredictable-MUL-arm.txt | ||
| unpredictable-MVN-arm.txt | ||
| unpredictable-RSC-arm.txt | ||
| unpredictable-SEL-arm.txt | ||
| unpredictable-SHADD16-arm.txt | ||
| unpredictable-SSAT-arm.txt | ||
| unpredictable-STRBrs-arm.txt | ||
| unpredictable-UQADD8-arm.txt | ||
| unpredictable-swp-arm.txt | ||
| unpredictables-thumb.txt | ||
| vfp4.txt | ||
| virtexts-arm.txt | ||
| virtexts-thumb.txt | ||
| vmrs-vmsr-invalid.txt | ||
| vscclrm.txt | ||
| vstrldr_sys.txt | ||