forked from OSchip/llvm-project
56e4ea2bff
microMIPS jump and link exchange instruction stores a target in a 26-bits field. Despite other microMIPS JAL instructions these bits are target address shifted right 2 bits [1]. The patch fixes the JALX instruction decoding and uses 2-bit shift. [1] MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set Differential Revision: https://reviews.llvm.org/D67320 llvm-svn: 371428 |
||
|---|---|---|
| .. | ||
| crc | ||
| dsp | ||
| dspr2 | ||
| eva | ||
| ginv | ||
| micromips-dsp | ||
| micromips-dspr2 | ||
| micromips-dspr3 | ||
| micromips32r3 | ||
| micromips32r6 | ||
| mips1 | ||
| mips2 | ||
| mips3 | ||
| mips4 | ||
| mips32 | ||
| mips32r2 | ||
| mips32r3 | ||
| mips32r5 | ||
| mips32r6 | ||
| mips64 | ||
| mips64r2 | ||
| mips64r3 | ||
| mips64r5 | ||
| mips64r6 | ||
| msa | ||
| mt | ||
| virt | ||
| lit.local.cfg | ||