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llvm-project/llvm/test/MC/Disassembler/ARM
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Alexandros Lamprineas c006b6f4cb [MC][ARM] vscclrm disassembles as vldmia 
Happens only when the mve.fp subtarget feature is enabled:

$ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b"
  .text
  vldmia  pc, {d0, d1, d2, d3}
$ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b"
  .text
  vscclrm {d0, d1, d2, d3, vpr}

Assembling returns the correct encoding with or without mve.fp:

$ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}"
  .text
  vscclrm {d0, d1, d2, d3, vpr}   @ encoding: [0x9f,0xec,0x08,0x0b]
$ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}"
  .text
  vscclrm {d0, d1, d2, d3, vpr}   @ encoding: [0x9f,0xec,0x08,0x0b]

The problem seems to be in the TableGen description of VSCCLRMD.
The least significant bit should be set to zero.

Differential Revision: https://reviews.llvm.org/D68025

llvm-svn: 373052
 		2019-09-27 08:22:24 +00:00
..
addrmode2-reencoding.txt
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arm-LDREXD-reencoding.txt
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arm-STREXD-reencoding.txt
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arm-tests.txt
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arm-thumb-trustzone.txt
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arm-trustzone.txt
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arm-vmrs_vmsr.txt [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode 2017-10-18 14:47:37 +00:00
armv8.1a.txt
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armv8.2a-dotprod-a32.s [ARM] Assembler support for the ARMv8.2a dot product instructions 2017-08-11 09:52:30 +00:00
armv8.2a-dotprod-t32.s [ARM] Assembler support for the ARMv8.2a dot product instructions 2017-08-11 09:52:30 +00:00
armv8.3a-js-arm.txt [ARM][AArch64] v8.3-A Javascript Conversion 2017-08-22 11:08:21 +00:00
armv8.3a-js-thumb.txt [ARM][AArch64] v8.3-A Javascript Conversion 2017-08-22 11:08:21 +00:00
armv8.4a-trace-a32.txt [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction 2018-07-06 08:03:12 +00:00
armv8.4a-trace-t32.txt [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction 2018-07-06 08:03:12 +00:00
armv8.5a-sb-thumb.txt [ARM] Add command-line option for SB 2019-01-03 12:09:12 +00:00
armv8.5a-sb.txt [NFC] Fix missing testfile change of rL350299 2019-01-03 12:48:06 +00:00
armv8a-fpmul-a32.txt [ARM/AArch64] Support FP16 +fp16fml instructions 2018-08-17 11:29:49 +00:00
armv8a-fpmul-t32.txt [ARM/AArch64] Support FP16 +fp16fml instructions 2018-08-17 11:29:49 +00:00
basic-arm-instructions-v8.txt
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basic-arm-instructions.txt [ARM][v8.5A] Add speculation barriers SSBB and PSSBB 2018-09-28 08:27:56 +00:00
clrm.txt [ARM] Add the non-MVE instructions in Arm v8.1-M. 2019-06-11 09:29:18 +00:00
coprocessors-arm.txt [ARM] Make coprocessor number restrictions consistent. 2019-06-27 12:40:55 +00:00
coprocessors-thumb.txt [ARM] Make coprocessor number restrictions consistent. 2019-06-27 12:40:55 +00:00
crc32-thumb.txt
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crc32.txt
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csdb-arm.txt [ARM][AArch64] Add CSDB speculation barrier instruction 2018-02-06 09:24:47 +00:00
csdb-thumb.txt [ARM][AArch64] Add CSDB speculation barrier instruction 2018-02-06 09:24:47 +00:00
d16.txt
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dfb-arm.txt [ARM] Armv8-R DFB instruction 2017-12-21 11:17:49 +00:00
dfb-thumb.txt [ARM] Armv8-R DFB instruction 2017-12-21 11:17:49 +00:00
fp-armv8.txt
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fp-encoding.txt
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fullfp16-arm-neg.txt
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fullfp16-arm-nopred.txt [ARM] Make fullfp16 instructions not conditionalisable. 2019-02-25 10:39:53 +00:00
fullfp16-arm.txt
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fullfp16-neon-arm-neg.txt
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fullfp16-neon-arm.txt
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fullfp16-neon-thumb-neg.txt
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fullfp16-neon-thumb.txt
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fullfp16-thumb-neg.txt
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fullfp16-thumb-nopred.txt [ARM] Make fullfp16 instructions not conditionalisable. 2019-02-25 10:39:53 +00:00
fullfp16-thumb.txt
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hex-immediates.txt
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invalid-FSTMX-arm.txt
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invalid-IT-CC15.txt ARM: correctly decode VFP instructions following unpredictable t2IT 2018-06-26 11:39:20 +00:00
invalid-armv7.txt [ARM][MC] Update one test case in 'test/MC/Disassembler/ARM/invalid-armv7.txt' 2019-03-05 03:07:56 +00:00
invalid-armv8.1a.txt
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invalid-armv8.txt
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invalid-because-armv7.txt
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invalid-thumb-MSR-MClass.txt [ARM]Decoding MSR with unpredictable destination register causes an assert 2018-03-06 15:21:19 +00:00
invalid-thumbv7-xfail.txt
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invalid-thumbv7.txt ARM: disallow add/sub to sp unless Rn is also sp. 2019-04-23 13:50:13 +00:00
invalid-thumbv8.1a.txt
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invalid-thumbv8.txt
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invalid-virtexts.arm.txt
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ldrd-armv4.txt
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lit.local.cfg [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
load-store-acquire-release-v8-thumb.txt
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load-store-acquire-release-v8.txt
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marked-up-thumb.txt
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memory-arm-instructions.txt
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move-banked-regs-arm.txt
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move-banked-regs-thumb.txt
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mve-bitops.txt [ARM] Add MVE vector bit-operations (register inputs). 2019-06-19 16:43:53 +00:00
mve-float.txt [ARM] Add a batch of MVE floating-point instructions. 2019-06-21 09:35:07 +00:00
mve-integer.txt [ARM] Add a batch of MVE integer instructions. 2019-06-20 15:16:56 +00:00
mve-interleave.txt [ARM] Add MVE interleaving load/store family. 2019-06-24 10:00:39 +00:00
mve-load-store.txt [ARM] Add MVE vector load/store instructions. 2019-06-25 11:24:18 +00:00
mve-minmax.txt [ARM] Add MVE integer vector min/max instructions. 2019-06-18 15:51:46 +00:00
mve-misc.txt [ARM] Fix handling of zero offsets in LOB instructions. 2019-06-27 12:41:07 +00:00
mve-qdest-qsrc.txt [ARM] Add a batch of similarly encoded MVE instructions. 2019-06-21 12:13:59 +00:00
mve-qdest-rsrc.txt [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH. 2019-07-11 09:52:15 +00:00
mve-reductions.txt [ARM] Remove some spurious MVE reduction instructions. 2019-09-09 15:17:26 +00:00
mve-scalar-shift-unpredictable.txt [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings 2019-09-09 08:50:28 +00:00
mve-scalar-shift.txt [ARM] Add <saturate> operand to SQRSHRL and UQRSHLL 2019-07-19 09:46:28 +00:00
mve-shifts.txt [ARM] Add MVE vector shift instructions. 2019-06-18 16:19:59 +00:00
mve-vcmp.txt [ARM] Add MVE vector compare instructions. 2019-06-21 11:14:51 +00:00
mve-vmov-lane.txt [ARM] Add MVE vector bit-operations (register inputs). 2019-06-19 16:43:53 +00:00
mve-vmov-pair.txt [ARM] Add MVE 64-bit GPR <-> vector move instructions. 2019-06-21 13:17:23 +00:00
mve-vpt.txt [ARM] Set up infrastructure for MVE vector instructions. 2019-06-13 13:11:13 +00:00
neon-complex-arm.txt [ARM] v8.3-a complex number support 2017-09-29 13:11:33 +00:00
neon-complex-thumb.txt [ARM] v8.3-a complex number support 2017-09-29 13:11:33 +00:00
neon-crypto.txt
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neon-tests.txt
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neon-v8.txt
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neon.txt
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neont-VLD-reencoding.txt
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neont-VST-reencoding.txt
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neont2.txt
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ras-extension-arm.txt
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ras-extension-thumb.txt [ARM] Extra MVE-related testing. 2019-06-25 11:24:42 +00:00
thumb-MSR-MClass.txt
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thumb-fp-armv8.txt
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thumb-neon-crypto.txt
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thumb-neon-v8.txt
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thumb-printf.txt
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thumb-tests.txt
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thumb-v8.1a.txt
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thumb-v8.txt
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thumb-vmrs_vmsr.txt [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode 2017-10-18 14:47:37 +00:00
thumb1.txt
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thumb2-bit-15.txt [ARM] Turn some undefined encoding bits into 0s. 2019-06-04 08:28:48 +00:00
thumb2-preloads.txt
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thumb2-v8.1m.txt [ARM] Fix handling of zero offsets in LOB instructions. 2019-06-27 12:41:07 +00:00
thumb2-v8.txt
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thumb2-v8m.txt
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thumb2.txt [ARM][v8.5A] Add speculation barriers SSBB and PSSBB 2018-09-28 08:27:56 +00:00
thumbv8.1m-vmrs-vmsr.txt [ARM] Add the non-MVE instructions in Arm v8.1-M. 2019-06-11 09:29:18 +00:00
thumbv8.1m.s [ARM] Reject CSEL instructions with invalid operands 2019-07-31 14:22:45 +00:00
unpredictable-ADC-arm.txt
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unpredictable-ADDREXT3-arm.txt
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unpredictable-AExtI-arm.txt
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unpredictable-AI1cmp-arm.txt
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unpredictable-BFI.txt
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unpredictable-LDR-arm.txt
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unpredictable-LDRD-arm.txt
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unpredictable-LSL-regform.txt
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unpredictable-MRRC2-arm.txt
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unpredictable-MRS-arm.txt
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unpredictable-MUL-arm.txt
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unpredictable-MVN-arm.txt [ARM] Add support for unpredictable MVN instructions. 2018-02-01 12:06:57 +00:00
unpredictable-RSC-arm.txt
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unpredictable-SEL-arm.txt
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unpredictable-SHADD16-arm.txt
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unpredictable-SSAT-arm.txt
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unpredictable-STRBrs-arm.txt
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unpredictable-UQADD8-arm.txt
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unpredictable-swp-arm.txt
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unpredictables-thumb.txt
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vfp4.txt
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virtexts-arm.txt
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virtexts-thumb.txt
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vmrs-vmsr-invalid.txt [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings 2019-09-03 09:55:30 +00:00
vscclrm.txt [MC][ARM] vscclrm disassembles as vldmia 2019-09-27 08:22:24 +00:00
vstrldr_sys.txt [ARM] Add the non-MVE instructions in Arm v8.1-M. 2019-06-11 09:29:18 +00:00