forked from OSchip/llvm-project
89 lines
3.7 KiB
ArmAsm
89 lines
3.7 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-8, 7].
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ldnf1h z21.h, p4/z, [x17, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnf1h z21.h, p4/z, [x17, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h z10.h, p5/z, [x16, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnf1h z10.h, p5/z, [x16, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h z30.s, p6/z, [x25, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnf1h z30.s, p6/z, [x25, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h z29.s, p5/z, [x15, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnf1h z29.s, p5/z, [x15, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h z28.d, p2/z, [x28, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnf1h z28.d, p2/z, [x28, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h z27.d, p1/z, [x26, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnf1h z27.d, p1/z, [x26, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// restricted predicate has range [0, 7].
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ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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ldnf1h { }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: ldnf1h { }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ldnf1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z21.d, p5/z, z28.d
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ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z21, z28
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ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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