forked from OSchip/llvm-project
183 lines
6.3 KiB
YAML
183 lines
6.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: insert_vector_elt_0_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; CHECK-LABEL: name: insert_vector_elt_0_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[COPY]], [[COPY1]](s32), 0
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; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$vgpr0_vgpr1 = COPY %3
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...
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---
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name: insert_vector_elt_1_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; CHECK-LABEL: name: insert_vector_elt_1_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[COPY]], [[COPY1]](s32), 32
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; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = G_CONSTANT i32 1
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%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$vgpr0_vgpr1 = COPY %3
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...
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---
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name: insert_vector_elt_2_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; CHECK-LABEL: name: insert_vector_elt_2_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
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; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = G_CONSTANT i32 2
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%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$vgpr0_vgpr1 = COPY %3
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...
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---
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name: insert_vector_elt_v2s32_varidx_i64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3_vgpr4
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; CHECK-LABEL: name: insert_vector_elt_v2s32_varidx_i64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr3_vgpr4
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
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; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[TRUNC]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[IVEC]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s64) = COPY $vgpr3_vgpr4
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%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$vgpr0_vgpr1 = COPY %3
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...
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---
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name: insert_vector_elt_v16s32_varidx_i64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16, $vgpr17_vgpr18
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; CHECK-LABEL: name: insert_vector_elt_v16s32_varidx_i64
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; CHECK: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr16
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr17_vgpr18
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
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; CHECK: [[IVEC:%[0-9]+]]:_(<16 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[TRUNC]](s32)
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; CHECK: S_ENDPGM 0, implicit [[IVEC]](<16 x s32>)
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%0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
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%1:_(s32) = COPY $vgpr16
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%2:_(s64) = COPY $vgpr17_vgpr18
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%3:_(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: insert_vector_elt_0_v16s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: insert_vector_elt_0_v16s64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[DEF:%[0-9]+]]:_(<16 x s64>) = G_IMPLICIT_DEF
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; CHECK: [[INSERT:%[0-9]+]]:_(<16 x s64>) = G_INSERT [[DEF]], [[COPY]](s64), 0
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; CHECK: S_ENDPGM 0, implicit [[INSERT]](<16 x s64>)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(<16 x s64>) = G_IMPLICIT_DEF
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(<16 x s64>) = G_INSERT_VECTOR_ELT %1, %0, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: insert_vector_elt_0_v2s32_s8
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; CHECK-LABEL: name: insert_vector_elt_0_v2s32_s8
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[COPY]], [[COPY1]](s32), 0
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; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s8) = G_CONSTANT i8 0
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%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$vgpr0_vgpr1 = COPY %3
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...
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---
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name: insert_vector_elt_0_v2i8_i32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: insert_vector_elt_0_v2i8_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[COPY1]], [[COPY2]](s32), 0
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; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY [[INSERT]](<2 x s32>)
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; CHECK: $vgpr0_vgpr1 = COPY [[COPY3]](<2 x s32>)
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%0:_(s32) = COPY $vgpr0
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%1:_(s8) = G_TRUNC %0
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%2:_(<2 x s8>) = G_IMPLICIT_DEF
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%3:_(s32) = G_CONSTANT i32 0
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%4:_(<2 x s8>) = G_INSERT_VECTOR_ELT %2, %1, %3
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%5:_(<2 x s32>) = G_ANYEXT %4
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$vgpr0_vgpr1 = COPY %5
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...
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---
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name: insert_vector_elt_v4s32_s32_look_through_trunc_0
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
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; CHECK-LABEL: name: insert_vector_elt_v4s32_s32_look_through_trunc_0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s32>) = G_INSERT [[COPY]], [[COPY1]](s32), 0
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](<4 x s32>)
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%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s32) = COPY $vgpr4
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%2:_(s64) = G_CONSTANT i64 0
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%3:_(s32) = G_TRUNC %2
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%4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %3
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
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...
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