..
GlobalISel
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
32-bit-local-address-space.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
InlineAsmCrash.ll
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
README
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SRSRC-GIT-clobber-check.mir
For PAL, make sure Scratch Buffer Descriptor do not clobber GIT pointer
2020-05-06 10:31:15 -04:00
aa-points-to-constant-memory.ll
AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory
2020-05-09 16:00:08 -04:00
accvgpr-copy.mir
AMDGPU: Add a few more missing test for AGPR tuple copying
2020-07-16 15:53:11 -04:00
add-debug.ll
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add.i16.ll
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
2019-12-17 18:54:27 +00:00
add.ll
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add.v2i16.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
add3.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
add_i1.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
add_i64.ll
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add_i128.ll
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add_shl.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
addrspacecast-captured.ll
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addrspacecast-constantexpr.ll
[FunctionAttrs] Annotate "willreturn" for intrinsics
2019-07-28 06:09:56 +00:00
addrspacecast.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
adjust-writemask-invalid-copy.ll
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agpr-register-count.ll
[AMDGPU] separate accounting for agprs
2019-10-02 00:26:58 +00:00
agpr-remat.ll
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
alignbit-pat.ll
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alloca.ll
AllocaInst should store Align instead of MaybeAlign.
2020-05-16 14:53:16 -07:00
always-uniform.ll
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amdgcn-ieee.ll
AMDGPU: Change pre-gfx9 implementation of fcanonicalize to mul
2020-04-23 15:24:13 -04:00
amdgcn-load-offset-from-reg.ll
[AMDGPU] Add Relocation Constant Support
2020-03-30 13:49:20 -04:00
amdgcn.bitcast.ll
AMDGPU: Fix v2i64<->v4f32 bitcast
2020-02-20 09:49:09 -05:00
amdgcn.private-memory.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
amdgpu-alias-analysis.ll
[BasicAA] Rename -disable-basicaa to -disable-basic-aa to be consistent with the canonical name "basic-aa"
2020-06-26 20:55:44 -07:00
amdgpu-codegenprepare-fdiv.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
amdgpu-codegenprepare-fold-binop-select.ll
[AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32
2020-07-08 19:14:48 +01:00
amdgpu-codegenprepare-i16-to-i32.ll
AMDGPU: Generate test checks
2020-01-20 20:03:45 -05:00
amdgpu-codegenprepare-idiv.ll
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
amdgpu-codegenprepare-mul24.ll
AMDGPU: Introduce a flag to disable mul24 intrinsic formation
2019-08-24 22:14:41 +00:00
amdgpu-function-calls-option.ll
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amdgpu-inline.ll
[AMDGPU] Tune inlining parameters for AMDGPU target (part 2)
2019-11-19 16:33:16 +03:00
amdgpu-mul24-knownbits.ll
[AMDGPU] simplifyI24 - replace GetDemandedBits with SimplifyMultipleUseDemandedBits
2020-02-20 12:03:08 +00:00
amdgpu-reloc-const.ll
[AMDGPU] Add Relocation Constant Support
2020-03-30 13:49:20 -04:00
amdgpu-shader-calling-convention.ll
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amdgpu-unroll-threshold.ll
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
amdgpu.private-memory.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
amdgpu.work-item-intrinsics.deprecated.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
amdhsa-trap-num-sgprs.ll
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
2020-06-24 00:39:41 +05:30
amdpal-cs.ll
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amdpal-elf.ll
[AMDGPU] Don't mark the .note section as ALLOC
2020-05-05 14:21:45 +02:00
amdpal-es.ll
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amdpal-gs.ll
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amdpal-hs.ll
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amdpal-ls.ll
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amdpal-msgpack-cs.ll
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amdpal-msgpack-es.ll
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amdpal-msgpack-gs.ll
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amdpal-msgpack-hs.ll
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amdpal-msgpack-ls.ll
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amdpal-msgpack-ps.ll
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amdpal-msgpack-psenable.ll
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amdpal-msgpack-vs.ll
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amdpal-ps.ll
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amdpal-psenable.ll
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amdpal-vs.ll
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amdpal.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
amdpal_scratch_mergedshader.ll
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and-gcn.ll
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and.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
and_or.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
andorbitset.ll
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andorn2.ll
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andorxorinvimm.ll
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annotate-kernel-features-hsa-call.ll
AMDGPU: Add IntrWillReturn to intrinsic definitions
2020-06-18 15:38:10 -04:00
annotate-kernel-features-hsa.ll
AMDGPU: Add IntrWillReturn to intrinsic definitions
2020-06-18 15:38:10 -04:00
annotate-kernel-features.ll
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anonymous-gv.ll
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any_extend_vector_inreg.ll
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anyext.ll
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are-loads-from-same-base-ptr.ll
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array-ptr-calc-i32.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
array-ptr-calc-i64.ll
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ashr.v2i16.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
asm-printer-check-vcc.mir
[amdgpu] Fix check of VCC.
2020-05-06 14:16:37 -04:00
at-least-one-def-value-assert.mir
[AMDGPU] Define 16 bit VGPR subregs
2020-03-31 11:49:06 -07:00
atomic_cmp_swap_local.ll
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atomic_load_add.ll
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atomic_load_local.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
atomic_load_sub.ll
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atomic_optimizations_buffer.ll
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
atomic_optimizations_global_pointer.ll
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
atomic_optimizations_local_pointer.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
atomic_store_local.ll
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atomicrmw-nand.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
attr-amdgpu-flat-work-group-size-v3.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
[AMDGPU] Fix getEUsPerCU for gfx10 in CU mode
2020-03-27 20:36:49 +00:00
attr-amdgpu-flat-work-group-size.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
attr-amdgpu-num-sgpr.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
attr-amdgpu-num-vgpr.ll
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attr-amdgpu-waves-per-eu.ll
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attr-unparseable.ll
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barrier-elimination.ll
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basic-branch.ll
[AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
2019-10-18 21:48:22 +00:00
basic-call-return.ll
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basic-loop.ll
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bfe-combine.ll
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bfe-patterns.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
bfe_uint.ll
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bfi_int.ll
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bfm.ll
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big_alu.ll
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bitcast-constant-to-vector.ll
[MachineScheduler] Reduce reordering due to mem op clustering
2020-01-14 19:19:02 +00:00
bitcast-v4f16-v4i16.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
bitcast-vector-extract.ll
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bitreverse-inline-immediates.ll
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bitreverse.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
br_cc.f16.ll
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branch-condition-and.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
branch-relax-bundle.ll
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branch-relax-spill.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
branch-relaxation-debug-info.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
branch-relaxation-inst-size-gfx10.ll
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branch-relaxation.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
branch-uniformity.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
break-smem-soft-clauses.mir
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break-vmem-soft-clauses.mir
[AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizer
2020-05-05 15:49:09 +01:00
bswap.ll
AMDGPU: Improve i16/v2i16 bswap
2020-02-14 09:53:22 -08:00
buffer-intrinsics-mmo-offsets.ll
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
buffer-schedule.ll
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bug-sdag-scheduler-cycle.ll
SelectionDAG: Fix bug in ClusterNeighboringLoads
2020-02-12 09:12:55 +01:00
bug-vopc-commute.ll
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build-vector-insert-elt-infloop.ll
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build-vector-packed-partial-undef.ll
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
build_vector.ll
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bundle-latency.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
bypass-div.ll
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
byval-frame-setup.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
call-argument-types.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
call-constant.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
call-constexpr.ll
[AMDGPU] Packed thread ids in function call ABI
2019-06-28 01:52:13 +00:00
call-encoding.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
call-graph-register-usage.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
call-preserved-registers.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
call-return-types.ll
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call-skip.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
call-to-kernel-undefined.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
call-to-kernel.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
call-waitcnt.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
call-waw-waitcnt.mir
AMDGPU: Avoid overwriting saved PC
2019-10-28 10:02:22 -07:00
call_fs.ll
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callee-frame-setup.ll
[AMDGPU] Allow spilling FP to memory
2020-05-11 16:42:59 -07:00
callee-special-input-sgprs-fixed-abi.ll
AMDGPU: Fix DAG divergence for implicit function arguments
2020-05-19 18:11:34 -04:00
callee-special-input-sgprs.ll
AMDGPU: Fix DAG divergence for implicit function arguments
2020-05-19 18:11:34 -04:00
callee-special-input-vgprs.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
calling-conventions.ll
AMDGPU: Allow i16 shader arguments
2020-01-27 06:55:32 -08:00
captured-frame-index.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
carryout-selection.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
cayman-loop-bug.ll
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cc-sgpr-limit.ll
[AMDGPU] Adjust number of SGPRs available in Calling Convention
2019-08-28 15:00:45 +00:00
cc-sgpr-over-limit.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
cc-update.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
cf-loop-on-constant.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
cf-stack-bug.ll
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cf_end.ll
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cgp-addressing-modes-flat.ll
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cgp-addressing-modes.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
cgp-bitfield-extract.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
chain-hi-to-lo.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
clamp-modifier.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
clamp-omod-special-case.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
clamp.ll
AMDGPU: Remove fp-exceptions feature
2020-05-29 15:19:59 -04:00
cluster-flat-loads-postra.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
cluster-flat-loads.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
cluster_stores.ll
[AMDGPU/MemOpsCluster] Compute `width` for `MIMG` instruction class.
2020-06-23 17:32:17 +05:30
cmp_shrink.mir
[AMDGPU] Avoid using s_cmpk when src0 is not register
2020-07-14 09:05:53 +01:00
cndmask-no-def-vcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
coalescer-extend-pruned-subrange.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
coalescer-identical-values-undef.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescer-subranges-another-copymi-not-live.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
coalescer-subranges-another-prune-error.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
coalescer-subranges-prune-kill-copy.mir
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coalescer-subreg-join.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
coalescer-subregjoin-fullcopy.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
coalescer-with-subregs-bad-identical.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
coalescer_distribute.ll
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coalescer_remat.ll
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coalescing-subreg-was-undef-but-became-def.mir
[AMDGPU] Add the test from D49097.
2020-05-20 14:34:51 +01:00
coalescing-with-subregs-in-loop-bug.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
code-object-v3.ll
[llvm-readobj] Include section name of notes.
2020-03-05 09:53:14 -08:00
codegen-prepare-addrmode-sext.ll
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collapse-endcf-broken.mir
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collapse-endcf.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
collapse-endcf.mir
[AMDGPU] Limit endcf-collapase to simple if
2020-04-07 10:27:23 -07:00
collapse-endcf2.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
combine-and-sext-bool.ll
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combine-cond-add-sub.ll
Revert "AMDGPU: Try to commute sub of boolean ext"
2019-12-13 12:49:06 +00:00
combine-ftrunc.ll
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combine_vloads.ll
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comdat.ll
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commute-compares.ll
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commute-shifts.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
commute_modifiers.ll
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complex-folding.ll
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computeKnownBits-scalar-to-vector-crash.ll
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computeNumSignBits-mul.ll
[AMDGPU] Update autogenerated checks
2019-12-17 16:48:02 +00:00
concat_vectors.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
constant-address-space-32bit.ll
AMDGPU: Fix folding immediate into readfirstlane through reg_sequence
2019-06-19 20:44:15 +00:00
constant-fold-imm-immreg.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
constant-fold-mi-operands.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
control-flow-fastregalloc.ll
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
control-flow-optnone.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
convergent-inlineasm.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
copy-illegal-type.ll
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal
2020-05-12 16:05:12 -07:00
copy-to-reg.ll
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couldnt-join-subrange-3.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
cross-block-use-is-not-abi-copy.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
cse-phi-incoming-val.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
csr-gfx10.ll
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ctlz.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
ctlz_zero_undef.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
ctpop.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
ctpop16.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
ctpop64.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
cttz_zero_undef.ll
[AMDGPU] Fix typos in performCtlz_CttzCombine()
2020-07-14 10:18:18 +01:00
cube.ll
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cvt_f32_ubyte.ll
[AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.
2020-05-04 16:42:25 +03:00
cvt_flr_i32_f32.ll
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cvt_rpi_i32_f32.ll
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dag-divergence.ll
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dagcomb-shuffle-vecextend-non2.ll
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dagcombine-reassociate-bug.ll
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dagcombine-select.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
dagcombine-setcc-select.ll
[AMDGPU] Automatically generate various tests. NFC
2019-08-23 17:58:49 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
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dce-disjoint-intervals.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
dead-lane.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
dead-machine-elim-after-dead-lane.ll
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
2020-01-14 19:26:15 -05:00
dead_copy.mir
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debug-value-scheduler-crash.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
debug-value.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
debug-value2.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
debug.ll
[AMDGPU] Fix +DumpCode to print an entry label for the first function
2019-06-27 08:19:28 +00:00
default-fp-mode.ll
AMDGPU: Add some tests for exotic denormal mode combinations
2020-04-02 17:17:12 -04:00
detect-dead-lanes.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
directive-amdgcn-target.ll
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disable_form_clauses.ll
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disconnected-predset-break-bug.ll
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div_i128.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
diverge-extra-formal-args.ll
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diverge-interp-mov-lower.ll
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diverge-switch-default.ll
[InstCombine] fix operands of shouldChangeType() for casted phi transform
2020-02-04 07:45:48 -05:00
divergence-at-use.ll
[AMDGPU] Add amdgpu_kernel for consistency with other tests
2019-07-29 11:48:17 +00:00
divergent-branch-uniform-condition.ll
[AMDGPU] add generated checks for some LIT tests
2020-03-03 11:47:05 +05:30
divrem24-assume.ll
[AMDGPU] Fix some tests that did not specify -mcpu
2020-02-17 14:02:32 +00:00
dpp_combine.ll
[AMDGPU] link dpp pseudos and real instructions on gfx10
2019-10-11 22:03:36 +00:00
dpp_combine.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
drop-mem-operand-move-smrd.ll
…
ds-combine-large-stride.ll
…
ds-combine-with-dependence.ll
…
ds-negative-offset-addressing-mode-loop.ll
AMDGPU: Increase vcc liveness scan threshold
2019-10-20 17:44:17 +00:00
ds-sub-offset.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
ds_read2.ll
[llvm] Fix yet more missing FileCheck colons
2020-04-13 10:49:19 -06:00
ds_read2_offset_order.ll
AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets
2020-01-24 19:45:56 -08:00
ds_read2_superreg.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
ds_read2st64.ll
…
ds_write2.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
ds_write2st64.ll
[AMDGPU] Bundle loads before post-RA scheduler
2020-01-24 11:33:38 -08:00
dynamic_stackalloc.ll
…
early-if-convert-cost.ll
…
early-if-convert.ll
AMDGPU: Fix backwards s_cselect_* operands
2020-05-27 09:26:09 -04:00
early-inline-alias.ll
…
early-inline.ll
…
early-tailduplicator-nophis.mir
TailDuplication: Clear NoPHIs property
2019-12-27 14:06:31 -05:00
elf-header-flags-mach.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
elf-header-flags-sram-ecc.ll
[AMDGPU] gfx908 target
2019-07-09 18:10:06 +00:00
elf-header-flags-xnack.ll
…
elf-header-osabi.ll
…
elf-notes.ll
…
elf.ll
[Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names
2020-03-16 07:42:04 -07:00
elf.metadata.ll
…
elf.r600.ll
[Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names
2020-03-16 07:42:04 -07:00
else.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
empty-function.ll
…
enable-no-signed-zeros-fp-math.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
endcf-loop-header.ll
…
endpgm-dce.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
enqueue-kernel.ll
…
exceed-max-sgprs.ll
…
expand-scalar-carry-out-select-user.ll
AMDGPU: Don't ignore carry out user when expanding add_co_pseudo
2020-07-06 14:28:01 -04:00
extend-bit-ops-i16.ll
…
extload-align.ll
…
extload-private.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
extload.ll
…
extract-lowbits.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
extract-subvector-equal-length.ll
AMDGPU: Remove optnone from a test
2019-10-19 01:34:59 +00:00
extract-subvector.ll
[AMDGPU] Fixed selection error for 64 bit extract_subvector
2020-05-18 14:17:59 -07:00
extract-vector-elt-build-vector-combine.ll
…
extract_subvector_vec4_vec3.ll
Revert "Revert "[MIR] Target specific MIR formating and parsing""
2020-01-08 20:03:29 -08:00
extract_vector_dynelt.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
extract_vector_elt-f16.ll
…
extract_vector_elt-f64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
extract_vector_elt-i8.ll
…
extract_vector_elt-i16.ll
…
extract_vector_elt-i64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
extractelt-to-trunc.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
fabs.f16.ll
…
fabs.f64.ll
…
fabs.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fadd-fma-fmul-combine.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
fadd.f16.ll
[AMDGPU] Precommit some scheduler related test updates
2020-02-28 11:20:58 +00:00
fadd.ll
…
fadd64.ll
…
fail-select-buffer-atomic-fadd.ll
AMDGPU: Fix incorrect selection of buffer atomic fadd
2020-06-05 14:34:15 -04:00
fast-unaligned-load-store.global.ll
[AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.
2020-05-04 16:42:25 +03:00
fast-unaligned-load-store.private.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
fcanonicalize-elimination.ll
AMDGPU: Remove fp-exceptions feature
2020-05-29 15:19:59 -04:00
fcanonicalize.f16.ll
AMDGPU: Change pre-gfx9 implementation of fcanonicalize to mul
2020-04-23 15:24:13 -04:00
fcanonicalize.ll
AMDGPU: Change pre-gfx9 implementation of fcanonicalize to mul
2020-04-23 15:24:13 -04:00
fceil.ll
…
fceil64.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
…
fcmp.ll
…
fcmp64.ll
…
fconst64.ll
…
fcopysign.f16.ll
…
fcopysign.f32.ll
…
fcopysign.f64.ll
…
fdiv-nofpexcept.ll
AMDGPU: Add test for fdiv nofpexcept preservation
2020-06-04 17:35:27 -04:00
fdiv.f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fdiv.f64.ll
…
fdiv.ll
[DAGCombiner] Require ninf for division estimation
2020-06-14 22:58:22 +08:00
fdiv32-to-rcp-folding.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fdot2.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fence-barrier.ll
AMDGPU: Increase vcc liveness scan threshold
2019-10-20 17:44:17 +00:00
fence-lds-read2-write2.ll
AMDGPU: Break read2/write2 search range on a memory fence
2020-04-24 15:53:30 -04:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
fexp.ll
[AMDGPU] Clean up update_llc_test_checks CodeGen tests
2019-10-24 17:35:33 -04:00
ffloor.f64.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
ffloor.ll
…
fix-frame-ptr-reg-copy-livein.ll
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
fix-sgpr-copies.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fix-vgpr-copies.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
fix-wwm-vgpr-copy.ll
…
flat-address-space.ll
[AMDGPU] allow multi-dword flat scratch access since GFX9
2020-01-17 10:47:03 -08:00
flat-error-unsupported-gpu-hsa.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
flat-for-global-subtarget-feature.ll
…
flat-load-clustering.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
flat-offset-bug.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
flat-scratch-reg.ll
…
flat_atomics.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
flat_atomics_i64.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
floor.ll
…
fma-combine.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fma.f64.ll
[AMDGPU] Improve fma.f64 test. NFC.
2019-09-25 18:50:34 +00:00
fma.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
fmac.sdwa.ll
[AMDGPU] Enable v4f16 and above for v_pk_fma instructions
2019-07-29 08:15:10 +00:00
fmad-formation-fmul-distribute-denormal-mode.ll
DAG: Fix wrong legality check for ISD::FMAD
2020-04-13 10:25:39 -07:00
fmad.ll
…
fmax.ll
…
fmax3.f64.ll
…
fmax3.ll
…
fmax_legacy.f16.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
fmax_legacy.f64.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
fmax_legacy.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
fmaxnum.f64.ll
…
fmaxnum.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fmaxnum.r600.ll
…
fmed3.ll
…
fmin.ll
…
fmin3.ll
…
fmin_fmax_legacy.amdgcn.ll
…
fmin_legacy.f16.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
fmin_legacy.f64.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
fmin_legacy.ll
[llvm] Fix yet more missing FileCheck colons
2020-04-13 10:49:19 -06:00
fminnum.f64.ll
AMDGPU: Change pre-gfx9 implementation of fcanonicalize to mul
2020-04-23 15:24:13 -04:00
fminnum.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fminnum.r600.ll
…
fmul-2-combine-multi-use.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fmul.f16.ll
…
fmul.ll
…
fmul64.ll
…
fmuladd.f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fmuladd.f32.ll
[NFC] Fixed typo in tests parameters
2020-07-15 22:09:01 +03:00
fmuladd.f64.ll
…
fmuladd.v2f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fnearbyint.ll
…
fneg-combines.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fneg-combines.si.ll
…
fneg-fabs.f16.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
fneg-fabs.f64.ll
…
fneg-fabs.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fneg-fold-legalize-dag-increase-insts.ll
DAG: Stop trying to fold FP -(x-y) -> y-x in getNode with nsz
2019-12-31 22:49:51 -05:00
fneg.f16.ll
…
fneg.f64.ll
…
fneg.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fold-cndmask.mir
…
fold-fi-mubuf.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
fold-fi-operand-shrink.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-fmul-to-neg-abs.ll
…
fold-imm-copy.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
fold-imm-f16-f32.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
fold-immediate-operand-shrink-with-carry.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-immediate-operand-shrink.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-immediate-output-mods.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
fold-implicit-operand.mir
…
fold-multiple.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
fold-operands-order.mir
…
fold-operands-remove-m0-redef.mir
AMDGPU: Erase redundant redefs of m0 in SIFoldOperands
2019-10-21 19:53:46 +00:00
fold-over-exec.mir
[AMDGPU] SIFoldOperands should not fold register acrocc the EXEC definition
2019-09-30 15:31:17 +00:00
fold-readlane.mir
[AMDGPU] Fix to 'Fold readlane from copy of SGPR or imm'
2019-08-13 18:57:55 +00:00
fold-reload-into-exec.mir
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
fold-reload-into-m0.mir
AMDGPU: Disallow spill folding with m0 copies
2019-10-30 14:56:33 -07:00
fold-sgpr-copy.mir
[AMDGPU] Enable SGPR copy folding
2019-10-25 15:08:30 -07:00
fold-sgpr-multi-imm.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
fold-vgpr-copy.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
fold_16bit_imm.mir
[AMDGPU] Fix FoldImmediate for 16 bit operand
2020-05-05 10:19:14 -07:00
fold_acc_copy_into_valu.mir
[AMDGPU] Fix illegal agpr use by VALU
2019-10-02 23:23:46 +00:00
force-alwaysinline-lds-global-address-codegen.ll
…
force-alwaysinline-lds-global-address.ll
AMDGPU: Hack out noinline on functions using LDS globals
2020-04-02 14:12:07 -04:00
fp-atomic-to-s_denormmode.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
fp-classify.ll
…
fp16_to_fp32.ll
…
fp16_to_fp64.ll
…
fp32_to_fp16.ll
…
fp_to_sint.f64.ll
…
fp_to_sint.ll
…
fp_to_uint.f64.ll
…
fp_to_uint.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
fpext-free.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fpext.f16.ll
…
fpext.ll
…
fpow.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
fptosi.f16.ll
…
fptoui.f16.ll
…
fptrunc.f16.ll
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
fptrunc.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
fract.f64.ll
…
fract.ll
…
frame-index-elimination.ll
[AMDGPU] Reuse register during frame index elimination
2020-03-20 00:19:15 -07:00
frame-lowering-entry-all-sgpr-used.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
frame-lowering-fp-adjusted.mir
[AMDGPU] Move frame pointer from s34 to s33
2020-03-19 15:35:16 -04:00
frem.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
fshl.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
fshr.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
fsqrt.f64.ll
…
fsqrt.ll
AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x)
2020-02-05 00:24:07 -05:00
fsub.f16.ll
…
fsub.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fsub64.ll
…
ftrunc.f64.ll
…
ftrunc.ll
…
function-args.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
function-call-relocs.ll
…
function-returns.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
gds-atomic.ll
AMDGPU: Support GDS atomics
2019-07-01 17:17:45 +00:00
gep-address-space.ll
…
gfx10-vop-literal.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
gfx902-without-xnack.ll
…
global-atomics-fp.ll
AMDGPU: Fix overriding global FP atomic feature predicates
2020-06-04 17:50:38 -04:00
global-constant.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
global-directive.ll
…
global-extload-i16.ll
…
global-load-store-atomics.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
global-saddr.ll
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
2020-06-24 00:39:41 +05:30
global-smrd-unknown.ll
…
global-variable-relocs.ll
…
global_atomics.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
global_atomics_i64.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
global_smrd.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
global_smrd_cfg.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
gv-const-addrspace.ll
…
gv-offset-folding.ll
…
gws-hazards.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
half.ll
[AMDGPU] Bundle loads before post-RA scheduler
2020-01-24 11:33:38 -08:00
hard-clauses.mir
[AMDGPU] Fix assertion failure in SIInsertHardClauses
2020-05-15 15:49:52 +01:00
hazard-buffer-store-v-interp.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hazard-hidden-bundle.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hazard-in-bundle.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hazard-inlineasm.mir
…
hazard-kill.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hazard.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hoist-cond.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
hsa-default-device.ll
…
hsa-fp-mode.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
hsa-func-align.ll
…
hsa-func.ll
…
hsa-globals.ll
…
hsa-group-segment.ll
…
hsa-metadata-deduce-ro-arg-v3.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-deduce-ro-arg.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-enqueue-kernel-v3.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-enqueue-kernel.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-from-llvm-ir-full-v3.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-from-llvm-ir-full.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-hidden-args-v3.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-hidden-args.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-hostcall-absent-v3.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-hostcall-absent.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-hostcall-present-v3.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-hostcall-present.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-images-v3.ll
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
hsa-metadata-images.ll
…
hsa-metadata-invalid-ocl-version-1-v3.ll
…
hsa-metadata-invalid-ocl-version-1.ll
…
hsa-metadata-invalid-ocl-version-2-v3.ll
…
hsa-metadata-invalid-ocl-version-2.ll
…
hsa-metadata-invalid-ocl-version-3-v3.ll
…
hsa-metadata-invalid-ocl-version-3.ll
…
hsa-metadata-kernel-code-props-v3.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
hsa-metadata-kernel-code-props.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
hsa-metadata-wavefrontsize.ll
[AMDGPU] gfx1010 wave32 metadata
2019-06-17 16:48:56 +00:00
hsa-note-no-func.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
hsa.ll
Revert "[AMDGPU] Don’t marke the .note section as ALLOC"
2020-02-21 16:08:30 -08:00
huge-private-buffer.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
i1-copies-rpo.mir
AMDGPU: Make fixing i1 copies robust against re-ordering
2019-06-27 16:56:44 +00:00
i1-copy-from-loop.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
i1-copy-implicit-def.ll
…
i1-copy-phi-uniform-branch.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
i1-copy-phi.ll
…
i1_copy_phi_with_phi_incoming_value.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
i8-to-double-to-float.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
icmp64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
idiv-licm.ll
[AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32
2020-07-08 19:14:48 +01:00
idot2.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
idot4s.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
idot4u.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
idot8s.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
idot8u.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
illegal-sgpr-to-vgpr-copy.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
image-attributes.ll
…
image-load-d16-tfe.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
image-resource-id.ll
…
image-schedule.ll
…
image_ls_mipmap_zero.ll
[AMDGPU] Optimize image_[load|store]_mip
2019-06-10 15:58:51 +00:00
img-nouse-adjust.ll
…
imm.ll
[AMDGPU] Regenerate immediate constant tests
2020-02-19 18:58:44 +00:00
imm16.ll
AMDGPU: Don't use 16-bit FP inline constants in integer operands
2020-06-17 19:14:10 -04:00
immv216.ll
AMDGPU: Don't use 16-bit FP inline constants in integer operands
2020-06-17 19:14:10 -04:00
implicit-def-muse.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
indirect-addressing-si-gfx9.ll
[AMDGPU] Always expand ext/insertelement with divergent idx
2020-05-20 15:51:29 -07:00
indirect-addressing-si-noopt.ll
[SDAG] fold extract_vector_elt with undef index
2019-10-25 19:27:26 -04:00
indirect-addressing-si-pregfx9.ll
[AMDGPU] Always expand ext/insertelement with divergent idx
2020-05-20 15:51:29 -07:00
indirect-addressing-si.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
indirect-addressing-term.ll
RegAllocFast: Record internal state based on register units
2020-06-03 16:51:46 -04:00
indirect-call.ll
AMDGPU: Fix fixed ABI SGPR arguments
2020-07-06 09:01:18 -04:00
indirect-private-64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
infer-addrpace-pipeline.ll
…
infer-uniform-load-shader.ll
AMDGPU: Fix not using scalar loads for global reads in shaders
2020-06-02 09:49:23 -04:00
infinite-loop-evergreen.ll
…
infinite-loop.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
inline-asm.ll
AMDGPU: Analyze divergence of inline asm
2020-02-03 12:42:16 -08:00
inline-attr.ll
AMDGPU: Stop setting attributes based on TargetOptions
2020-03-27 13:13:43 -07:00
inline-calls.ll
…
inline-constraints.ll
[AMDGPU][CODEGEN] Added support of new inline assembler constraints
2020-07-02 17:20:15 +03:00
inline-maxbb.ll
[AMDGPU] Don't constrain callees with inlinehint from inlining on MaxBB check
2019-06-14 16:37:33 +00:00
inlineasm-16.ll
…
inlineasm-illegal-type.ll
…
inlineasm-packed.ll
…
input-mods.ll
…
insert-branch-w32.mir
[AMDGPU] Make sure to fix implicit operands on insertBranch
2020-06-24 16:50:48 +01:00
insert-skip-from-vcc.mir
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
insert-skips-flat-vmem.mir
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
insert-skips-gws.mir
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
insert-skips-ignored-insts.mir
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
insert-skips-kill-uncond.mir
[AMDGPU] Unify early PS termination blocks
2020-07-03 09:58:05 +09:00
insert-subvector-unused-scratch.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
insert-waitcnts-callee.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
insert-waitcnts-exp.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
insert_subreg.ll
…
insert_vector_dynelt.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
insert_vector_elt.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
insert_vector_elt.v2i16.ll
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
[AMDGPU] Precommit some scheduler related test updates
2020-02-28 11:20:58 +00:00
insert_vector_elt.v2i16.subtest-saddr.ll
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
inserted-wait-states.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
internalize.ll
…
invalid-addrspacecast.ll
AMDGPU: Lower addrspacecast to 32-bit constant
2020-05-08 10:46:00 -04:00
invalid-alloca.ll
Infer alignment of unmarked loads in IR/bitcode parsing.
2020-05-14 13:03:50 -07:00
invariant-load-no-alias-store.ll
…
invert-br-undef-vcc.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
ipra-regmask.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
ipra.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
jump-address.ll
…
kcache-fold.ll
…
kernarg-stack-alignment.ll
…
kernel-args.ll
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
2020-06-24 00:39:41 +05:30
kernel-argument-dag-lowering.ll
AMDGPU: Fix crash on v3i15 kernel arguments
2020-02-11 18:11:39 -05:00
kill-infinite-loop.ll
[AMDGPU] Insert PS early exit at end of control flow
2020-07-03 14:04:34 +09:00
known-never-nan.ll
…
known-never-snan.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
knownbits-recursion.ll
…
large-alloca-compute.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
large-alloca-graphics.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
lcssa-optnone.ll
[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs.
2019-07-25 14:50:18 +00:00
lds-alignment.ll
…
lds-bounds.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
lds-branch-vmem-hazard.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
lds-global-non-entry-func.ll
AMDGPU: Don't hard error on LDS globals in functions
2020-03-11 15:34:11 -04:00
lds-initializer.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
lds-m0-init-in-loop.ll
…
lds-misaligned-bug.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-relocs.ll
AMDGPU: Support commuting register and global operand
2020-07-01 13:59:13 -04:00
lds-size.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
lds-zero-initializer.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
lds_atomic_f32.ll
…
legalize-fp-load-invariant.ll
…
legalizedag-bug-expand-setcc.ll
…
limit-coalesce.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
lit.local.cfg
…
literals.ll
…
liveness.mir
…
llvm.amdgcn.alignb.ll
…
llvm.amdgcn.atomic.csub.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
llvm.amdgcn.atomic.dec.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
llvm.amdgcn.atomic.fadd.ll
AMDGPU: Fix overriding global FP atomic feature predicates
2020-06-04 17:50:38 -04:00
llvm.amdgcn.atomic.inc.ll
[SelectionDAG] Propagate alias metadata to target intrinsic nodes
2019-07-03 14:33:29 +00:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
llvm.amdgcn.ballot.i64.ll
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
llvm.amdgcn.buffer.atomic.ll
…
llvm.amdgcn.buffer.load.dwordx3.ll
…
llvm.amdgcn.buffer.load.format.d16.ll
…
llvm.amdgcn.buffer.load.format.ll
…
llvm.amdgcn.buffer.load.ll
AMDGPU: Fold frame index into MUBUF
2019-06-24 14:53:56 +00:00
llvm.amdgcn.buffer.store.dwordx3.ll
…
llvm.amdgcn.buffer.store.format.d16.ll
…
llvm.amdgcn.buffer.store.format.ll
…
llvm.amdgcn.buffer.store.ll
…
llvm.amdgcn.buffer.wbinvl1.ll
…
llvm.amdgcn.buffer.wbinvl1.sc.ll
…
llvm.amdgcn.buffer.wbinvl1.vol.ll
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
llvm.amdgcn.class.f16.ll
…
llvm.amdgcn.class.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
…
llvm.amdgcn.cubeid.ll
…
llvm.amdgcn.cubema.ll
…
llvm.amdgcn.cubesc.ll
…
llvm.amdgcn.cubetc.ll
…
llvm.amdgcn.cvt.pk.i16.ll
…
llvm.amdgcn.cvt.pk.u16.ll
…
llvm.amdgcn.cvt.pknorm.i16.ll
…
llvm.amdgcn.cvt.pknorm.u16.ll
…
llvm.amdgcn.cvt.pkrtz.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
llvm.amdgcn.dispatch.id.ll
…
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fixup.f16.ll
…
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.div.scale.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.ds.append.ll
AMDGPU/GlobalISel: Select DS append/consume
2020-01-17 20:09:53 -05:00
llvm.amdgcn.ds.bpermute.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.ds.consume.ll
AMDGPU/GlobalISel: Select DS append/consume
2020-01-17 20:09:53 -05:00
llvm.amdgcn.ds.gws.barrier.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
llvm.amdgcn.ds.gws.init.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.sema.br.ll
AMDGPU: Don't rely on m0 being -1 for GWS offsets
2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.p.ll
AMDGPU: Don't rely on m0 being -1 for GWS offsets
2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.release.all.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
llvm.amdgcn.ds.gws.sema.v.ll
AMDGPU: Don't rely on m0 being -1 for GWS offsets
2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.ordered.add.gfx10.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.ds.ordered.add.ll
AMDGPU: Don't error on ds.ordered intrinsic in function
2020-01-24 13:06:44 -08:00
llvm.amdgcn.ds.ordered.swap.ll
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
2020-01-14 19:26:15 -05:00
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.swizzle.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.exp.compr.ll
…
llvm.amdgcn.exp.ll
[AMDGPU] Strengthen export cluster ordering
2020-05-13 23:07:37 +09:00
llvm.amdgcn.exp.prim.ll
…
llvm.amdgcn.fcmp.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.fmad.ftz.f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
llvm.amdgcn.fmad.ftz.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
…
llvm.amdgcn.frexp.exp.f16.ll
…
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.groupstaticsize.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
llvm.amdgcn.icmp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.image.a16.dim.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.a16.encode.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.atomic.dim.ll
AMDGPU: Add/Fix tests for image atomic intrinsic.
2020-03-05 12:18:15 -05:00
llvm.amdgcn.image.d16.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.dim.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.gather4.d16.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.gather4.o.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.getlod.dim.ll
…
llvm.amdgcn.image.load.a16.d16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.load.a16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.msaa.load.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
llvm.amdgcn.image.nsa.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.a16.dim.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.sample.d16.dim.ll
[AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizer
2020-05-05 15:49:09 +01:00
llvm.amdgcn.image.sample.dim.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
llvm.amdgcn.image.sample.g16.encode.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
llvm.amdgcn.image.sample.ltolz.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.o.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.store.a16.d16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.store.a16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
…
llvm.amdgcn.implicit.buffer.ptr.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
llvm.amdgcn.implicitarg.ptr.ll
AMDGPU: Fix DAG divergence for implicit function arguments
2020-05-19 18:11:34 -04:00
llvm.amdgcn.init.exec.ll
AMDGPU/GlobalISel: Add support for init.exec intrinsics
2019-10-01 02:07:25 +00:00
llvm.amdgcn.init.exec.wave32.ll
AMDGPU/GlobalISel: Add support for init.exec intrinsics
2019-10-01 02:07:25 +00:00
llvm.amdgcn.interp.f16.ll
AMDGPU: Use CopyToReg for interp intrinsic lowering
2019-10-21 19:53:49 +00:00
llvm.amdgcn.interp.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
llvm.amdgcn.is.private.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.is.shared.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.kernarg.segment.ptr.ll
…
llvm.amdgcn.kill.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.ldexp.f16.ll
…
llvm.amdgcn.ldexp.ll
…
llvm.amdgcn.lerp.ll
…
llvm.amdgcn.log.clamp.ll
…
llvm.amdgcn.mbcnt.ll
…
llvm.amdgcn.mfma.ll
AMDGPU: Fix lit test checks with dag option
2019-11-28 10:01:06 +00:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Fixed dpp test. NFC.
2019-11-13 16:38:54 -08:00
llvm.amdgcn.mov.dpp8.ll
[AMDGPU] gfx1010 dpp16 and dpp8
2019-06-12 18:02:41 +00:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.mul.i24.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
llvm.amdgcn.mul.u24.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
llvm.amdgcn.permlane.ll
AMDGPU/GlobalISel: Select permlane16/permlanex16
2020-01-29 17:55:31 -05:00
llvm.amdgcn.ps.live.ll
…
llvm.amdgcn.qsad.pk.u16.u8.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.buffer.atomic.ll
AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}
2019-08-05 09:36:06 +00:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
…
llvm.amdgcn.raw.buffer.load.format.ll
…
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] New SIInsertHardClauses pass
2020-05-14 18:54:49 +01:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.buffer.store.format.ll
…
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll
…
llvm.amdgcn.raw.tbuffer.load.ll
…
llvm.amdgcn.raw.tbuffer.store.d16.ll
…
llvm.amdgcn.raw.tbuffer.store.ll
…
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
llvm.amdgcn.readfirstlane.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
llvm.amdgcn.readlane.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
llvm.amdgcn.s.buffer.load.ll
AMDGPU: Fix broken check lines
2020-04-02 18:52:49 -04:00
llvm.amdgcn.s.dcache.inv.ll
…
llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.get.waveid.in.workgroup.ll
…
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
…
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
…
llvm.amdgcn.s.memtime.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
llvm.amdgcn.s.setreg.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.waitcnt.ll
AMDGPU: s_waitcnt field should be treated as unsigned
2019-07-11 23:42:57 +00:00
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll
…
llvm.amdgcn.sdot2.ll
[AMDGPU] gfx908 dot instruction support
2019-07-11 00:00:27 +00:00
llvm.amdgcn.sdot4.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
llvm.amdgcn.sdot8.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
llvm.amdgcn.sendmsg.ll
[AMDGPU][MC] Enabled constant expressions as operands of sendmsg
2019-06-28 14:14:02 +00:00
llvm.amdgcn.set.inactive.ll
…
llvm.amdgcn.sffbh.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
…
llvm.amdgcn.softwqm.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
llvm.amdgcn.sqrt.f16.ll
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
llvm.amdgcn.sqrt.ll
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
llvm.amdgcn.struct.buffer.atomic.ll
AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}
2019-08-05 09:36:06 +00:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.load.ll
AMDGPU: Correct behavior of f16 buffer loads
2019-08-05 15:59:07 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.store.format.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.store.ll
AMDGPU: Correct behavior of f16/i16 non-format store intrinsics
2019-08-05 14:57:59 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll
…
llvm.amdgcn.struct.tbuffer.load.ll
…
llvm.amdgcn.struct.tbuffer.store.d16.ll
…
llvm.amdgcn.struct.tbuffer.store.ll
…
llvm.amdgcn.tbuffer.load.d16.ll
…
llvm.amdgcn.tbuffer.load.dwordx3.ll
…
llvm.amdgcn.tbuffer.load.ll
…
llvm.amdgcn.tbuffer.store.d16.ll
…
llvm.amdgcn.tbuffer.store.dwordx3.ll
…
llvm.amdgcn.tbuffer.store.ll
…
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal
2020-05-12 16:05:12 -07:00
llvm.amdgcn.udot2.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot4.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot8.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.ll
[AMDGPU] Support mov dpp with 64 bit operands
2019-10-15 16:41:15 +00:00
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.wavefrontsize.ll
[AMDGPU] gfx1010 wavefrontsize intrinsic folding
2019-06-17 17:57:50 +00:00
llvm.amdgcn.workgroup.id.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.amdgcn.workitem.id.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.amdgcn.wqm.vote.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote
2020-01-07 10:15:29 -05:00
llvm.amdgcn.writelane.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
llvm.ceil.f16.ll
…
llvm.cos.f16.ll
AMDGPU: Fix not using f16 fsin/fcos
2020-01-27 08:59:59 -08:00
llvm.cos.ll
…
llvm.dbg.value.ll
…
llvm.exp2.f16.ll
…
llvm.exp2.ll
…
llvm.floor.f16.ll
…
llvm.fma.f16.ll
[AMDGPU] Enable v4f16 and above for v_pk_fma instructions
2019-07-29 08:15:10 +00:00
llvm.fmuladd.f16.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.log.f16.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
llvm.log.ll
…
llvm.log2.f16.ll
…
llvm.log2.ll
…
llvm.log10.f16.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
llvm.log10.ll
…
llvm.maxnum.f16.ll
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal
2020-05-12 16:05:12 -07:00
llvm.memcpy.ll
[ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr
2020-02-03 22:49:30 +00:00
llvm.minnum.f16.ll
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal
2020-05-12 16:05:12 -07:00
llvm.mulo.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.pow.ll
…
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll
…
llvm.rint.f64.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.rint.ll
…
llvm.round.f64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.round.ll
…
llvm.sin.f16.ll
AMDGPU: Fix not using f16 fsin/fcos
2020-01-27 08:59:59 -08:00
llvm.sin.ll
[AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS
2020-05-31 05:21:55 +01:00
llvm.sqrt.f16.ll
…
llvm.trunc.f16.ll
…
lo16-32bit-physreg-copy.mir
[AMDGPU] fix copies between 32 and 16 bit
2020-05-04 08:54:22 -07:00
lo16-hi16-illegal-copy.mir
[AMDGPU] Drop 16 bit subreg suffixes on print
2020-05-06 08:14:10 -07:00
lo16-hi16-physreg-copy.mir
[AMDGPU] copyPhysReg() for 16 bit SGPR subregs
2020-04-17 11:59:39 -07:00
lo16-lo16-physreg-copy-agpr.mir
[AMDGPU] Define AGPR subregs
2020-04-28 15:30:43 -07:00
lo16-lo16-physreg-copy-sgpr.mir
[AMDGPU] copyPhysReg() for 16 bit SGPR subregs
2020-04-17 11:59:39 -07:00
load-constant-f32.ll
…
load-constant-f64.ll
…
load-constant-i1.ll
…
load-constant-i8.ll
…
load-constant-i16.ll
…
load-constant-i32.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
load-constant-i64.ll
…
load-global-f32.ll
…
load-global-f64.ll
…
load-global-i1.ll
…
load-global-i8.ll
…
load-global-i16.ll
…
load-global-i32.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
load-global-i64.ll
…
load-hi16.ll
[AMDGPU] Define 16 bit VGPR subregs
2020-03-31 11:49:06 -07:00
load-input-fold.ll
…
load-lo16.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
load-local-f32-no-ds128.ll
…
load-local-f32.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-f64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-i1.ll
…
load-local-i8.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-i16.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-i32.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-i64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-select-ptr.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
load-weird-sizes.ll
…
local-64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
local-atomics-fp.ll
…
local-atomics.ll
…
local-atomics64.ll
…
local-memory.amdgcn.ll
[AMDGPU] Bundle loads before post-RA scheduler
2020-01-24 11:33:38 -08:00
local-memory.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
local-memory.r600.ll
…
local-stack-slot-offset.ll
…
loop-address.ll
…
loop-idiom.ll
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
loop-prefetch.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
loop_break.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
loop_exit_with_xor.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
loop_header_nopred.mir
[MBP] Avoid tail duplication if it can't bring benefit
2019-12-06 09:53:53 -08:00
lower-kernargs.ll
AllocaInst should store Align instead of MaybeAlign.
2020-05-16 14:53:16 -07:00
lower-mem-intrinsics-threshold.ll
AMDGPU: Add flag to control mem intrinsic expansion
2020-02-03 14:26:01 -08:00
lower-mem-intrinsics.ll
AMDGPU: Implement getMemcpyLoopLoweringType
2020-03-30 22:21:01 +01:00
lower-range-metadata-intrinsic-call.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
lshl64-to-32.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
lshr.v2i16.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
machine-cse-commute-target-flags.mir
AMDGPU: Support commuting register and global operand
2020-07-01 13:59:13 -04:00
macro-fusion-cluster-vcc-uses.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
mad-combine.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
mad-mix-hi.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
mad-mix-lo.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
mad-mix.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
mad.u16.ll
…
mad24-get-global-id.ll
…
mad_64_32.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
mad_int24.ll
AMDGPU: Combine directly on mul24 intrinsics
2019-08-27 00:18:09 +00:00
mad_uint24.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
madak-inline-constant.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
madak.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
madmk.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
mai-hazards.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
mai-inline.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
max-literals.ll
…
max-sgprs.ll
…
max.i16.ll
[AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.
2020-05-04 16:42:25 +03:00
max.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
max3.ll
…
mcp-overlap-after-propagation.mir
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
med3-no-simplify.ll
…
mem-builtins.ll
…
memcpy-inline-fails.ll
Revert "Disable memcpy-inline-fails.ll for windows"
2020-03-16 16:03:39 +01:00
memory-legalizer-amdpal.ll
[AMDGPU] Skip generating cache invalidating instructions on AMDPAL
2020-04-24 13:53:44 +02:00
memory-legalizer-atomic-cmpxchg.ll
…
memory-legalizer-atomic-fence.ll
…
memory-legalizer-atomic-insert-end.mir
llc: Change behavior of -mcpu with existing attribute
2020-01-07 10:10:25 -05:00
memory-legalizer-atomic-rmw.ll
…
memory-legalizer-invalid-addrspace.mir
…
memory-legalizer-invalid-syncscope.ll
…
memory-legalizer-load.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
memory-legalizer-local.mir
…
memory-legalizer-mesa3d.ll
…
memory-legalizer-multiple-mem-operands-atomics.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
memory-legalizer-region.mir
…
memory-legalizer-store-infinite-loop.ll
…
memory-legalizer-store.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
memory_clause.ll
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
2020-06-24 00:39:41 +05:30
memory_clause.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
merge-image-load-gfx10.mir
SILoadStoreOptimizer: add support for GFX10 image instructions
2020-07-08 19:15:46 +01:00
merge-image-load.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
merge-image-sample-gfx10.mir
SILoadStoreOptimizer: add support for GFX10 image instructions
2020-07-08 19:15:46 +01:00
merge-image-sample.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
merge-load-store-physreg.mir
AMDGPU: Remove unnecessary IR from test
2019-10-14 18:30:29 +00:00
merge-load-store-vreg.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
merge-load-store.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
merge-m0.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
merge-out-of-order-ldst.ll
[AMDGPU] Fix crash in SILoadStoreOptimizer
2020-04-02 10:26:47 -07:00
merge-out-of-order-ldst.mir
[AMDGPU] Fix crash in SILoadStoreOptimizer
2020-04-02 10:26:47 -07:00
merge-store-crash.ll
[AMDGPU] Bundle loads before post-RA scheduler
2020-01-24 11:33:38 -08:00
merge-store-usedef.ll
…
merge-stores.ll
[ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr
2020-02-03 22:49:30 +00:00
merge-tbuffer.mir
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
mesa3d.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
mesa_regression.ll
…
mfma-loop.ll
[AMDGPU] Added label to test. NFC.
2020-04-03 11:36:32 -07:00
min.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
min3.ll
…
mir-print-dead-csr-fi.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
misched-killflags.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
missing-store.ll
…
mixed-wave32-wave64.ll
[AMDGPU] gfx10 tests. NFC.
2019-06-20 16:29:40 +00:00
mixed_wave32_wave64.ll
[AMDGPU] gfx10 tests. NFC.
2019-06-20 16:29:40 +00:00
mode-register.mir
[AMDGPU] Avoid redundant mode register writes
2020-06-24 14:11:29 +01:00
move-addr64-rsrc-dead-subreg-writes.ll
…
move-to-valu-atomicrmw.ll
…
move-to-valu-worklist.ll
…
movreld-bug.ll
AMDGPU: Add gfx9 run lines to a testcase
2020-01-03 15:25:50 -05:00
movrels-bug.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
mubuf-legalize-operands.ll
[AMDGPU] Remove unnecessary s_waitcnt between VMEM loads
2020-05-01 10:10:23 +01:00
mubuf-legalize-operands.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
mubuf-offset-private.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
mubuf-shader-vgpr.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
mubuf.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
mul.i16.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
mul.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
mul24-pass-ordering.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
mul_int24.ll
…
mul_uint24-amdgcn.ll
[AMDGPU] Fix bundle scheduling
2020-01-09 15:56:36 -08:00
mul_uint24-r600.ll
…
multi-divergent-exit-region.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
multi-dword-vgpr-spill.ll
…
multilevel-break.ll
[AMDGPU] Enable structurizer workarounds by default
2020-06-09 13:14:15 +05:30
nand.ll
…
nested-calls.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
nested-loop-conditions.ll
[AMDGPU] Enable structurizer workarounds by default
2020-06-09 13:14:15 +05:30
no-bundle-asm.ll
AMDGPU: Do not bundle inline asm
2020-06-14 13:24:50 -04:00
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll
Use -mtriple to fix AMDGPU test sensitive to object file format
2019-09-05 00:34:01 +00:00
no-remat-indirect-mov.mir
AMDGPU: Don't run indexing mode switches with exec = 0
2020-06-02 13:47:48 -04:00
no-shrink-extloads.ll
…
non-entry-alloca.ll
AMDGPU: Fix alignment for dynamic allocas
2020-06-01 13:06:37 -04:00
noop-shader-O0.ll
…
nop-data.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
nop-fold.mir
AMDGPU: Don't fold S_NOPs with implicit operands
2019-10-30 14:40:56 -07:00
nor.ll
…
not-scalarize-volatile-load.ll
…
nsa-reassign.ll
[AMDGPU] Precommit some scheduler related test updates
2020-02-28 11:20:58 +00:00
nsa-vmem-hazard.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
nullptr.ll
AMDGPU: Fix wrong null value for private address space
2020-05-26 16:35:13 -04:00
occupancy-levels.ll
AMDGPU: Fix computation for getOccupancyWithLocalMemSize
2020-03-03 17:15:57 -05:00
offset-split-flat.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
offset-split-global.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
omod-nsz-flag.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
omod.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
opencl-image-metadata.ll
…
opencl-printf-no-hostcall.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
opencl-printf.ll
[AMDGPU] Printf runtime binding pass
2019-08-12 17:12:29 +00:00
operand-folding.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
operand-spacing.ll
…
opt-pipeline.ll
[LPM] Port CGProfilePass from NPM to LPM
2020-07-10 09:04:51 -07:00
opt-sgpr-to-vgpr-copy.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
optimize-exec-masking-pre-ra.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-if-exec-masking.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
optimize-negated-cond-exec-masking-wave32.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-negated-cond-exec-masking.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-negated-cond.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
or.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
or3.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
pack.v2f16.ll
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
pack.v2i16.ll
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
packed-op-sel.ll
[AMDGPU] Fix bundle scheduling
2020-01-09 15:56:36 -08:00
packetizer.ll
…
pal-userdata-regs.ll
[AMDGPU] Fixed incorrect PAL metadata register naming
2020-05-21 22:13:19 +01:00
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
partial-sgpr-to-vgpr-spills.ll
RegAllocFast: Record internal state based on register units
2020-06-03 16:51:46 -04:00
partial-shift-shrink.ll
…
partially-dead-super-register-immediate.ll
…
peephole-opt-regseq-removal.mir
…
pei-reg-scavenger-position.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
pei-scavenge-sgpr-carry-out.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
pei-scavenge-sgpr-gfx9.mir
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
pei-scavenge-sgpr.mir
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
pei-scavenge-vgpr-spill.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
perfhint.ll
…
permute.ll
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
phi-elimination-assertion.mir
[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed
2019-09-17 09:08:58 +00:00
phi-elimination-end-cf.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
phi-vgpr-input-moveimm.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
pk_max_f16_literal.ll
…
post-ra-sched-kill-bundle-use-inst.mir
ScheduleDAG: Fix incorrectly killing registers in bundles
2019-07-05 15:32:28 +00:00
postra-bundle-memops.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
postra-machine-sink.mir
[AMDGPU] Fixed lane mask in test. NFC.
2020-04-15 15:26:53 -07:00
postra-norename.mir
…
power-sched-no-instr-sunit.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
predicate-dp4.ll
…
predicates.ll
…
preserve-hi16.ll
AMDGPU: Fix i16 arithmetic pattern redundancy
2019-10-08 17:36:38 +00:00
print-mir-custom-pseudo.ll
…
private-access-no-objects.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
private-element-size.ll
[SelectionDAG] Don't promote the alignment of allocas beyond the stack alignment.
2020-05-11 17:39:00 -07:00
private-memory-atomics.ll
…
private-memory-r600.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-addrspacecast.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-calling-conv.ll
…
promote-alloca-globals.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
promote-alloca-invariant-markers.ll
…
promote-alloca-lifetime.ll
AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca
2019-06-18 12:23:44 +00:00
promote-alloca-mem-intrinsics.ll
…
promote-alloca-no-opts.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
promote-alloca-padding-size-estimate.ll
…
promote-alloca-pointer-array.ll
[AMDGPU] Fixed promote alloca with ptr/int casts
2020-06-10 11:46:57 -07:00
promote-alloca-stored-pointer-value.ll
…
promote-alloca-to-lds-icmp.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-to-lds-phi.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-to-lds-select.ll
[ValueTracking, BasicAA] Don't simplify instructions
2020-06-21 16:31:07 +02:00
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-vector-to-vector.ll
[AMDGPU] Bail alloca vectorization if GEP not found
2020-05-26 13:59:49 -07:00
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
promote-constOffset-to-imm.ll
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
2020-06-24 00:39:41 +05:30
promote-constOffset-to-imm.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
propagate-attributes-bitcast-function.ll
[test] Fix tests when run on windows after SVN r369426. NFC.
2019-08-20 20:58:02 +00:00
propagate-attributes-clone.ll
[AMDGPU] Propagate amdgpu-waves-per-eu to callees
2020-03-26 14:43:44 -07:00
propagate-attributes-single-set.ll
[test] Fix tests when run on windows after SVN r369426. NFC.
2019-08-20 20:58:02 +00:00
ptrmask.ll
DAG: Use correct pointer size for llvm.ptrmask
2020-05-18 16:46:11 -04:00
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll
R600: Fix failing testcase
2020-01-22 16:01:35 -05:00
r600-encoding.ll
…
r600-export-fix.ll
[AMDGPU] Automatically generate various tests. NFC
2019-08-23 17:58:49 +00:00
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
…
r600.add.ll
…
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
Regenerate bitcast test for upcoming patch.
2020-02-02 18:27:44 +00:00
r600.extract-lowbits.ll
…
r600.func-alignment.ll
…
r600.global_atomics.ll
…
r600.private-memory.ll
…
r600.sub.ll
…
r600.work-item-intrinsics.ll
…
r600cfg.ll
…
rcp-pattern.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
rcp_iflag.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
read-register-invalid-subtarget.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
read-register-invalid-type-i32.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
read-register-invalid-type-i64.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
read_register.ll
AMDGPU: Adjust test so it will work with GlobalISel
2019-12-27 19:37:39 -05:00
readcyclecounter.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
readlane_exec0.mir
…
reassoc-scalar.ll
…
reduce-build-vec-ext-to-ext-build-vec.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
reduce-load-width-alignment.ll
…
reduce-saveexec.mir
…
reduce-store-width-alignment.ll
…
reduction.ll
DAG: Combine extract_vector_elt of concat_vectors
2020-04-06 09:26:29 -04:00
reg-coalescer-sched-crash.ll
…
regbank-reassign.mir
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
regcoal-subrange-join-seg.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
regcoal-subrange-join.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
regcoalesce-cannot-join-failures.mir
…
regcoalesce-dbg.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
…
regcoalesce-prune.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
regcoalescing-remove-partial-redundancy-assert.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
register-count-comments.ll
…
rel32.ll
[amdgpu] Fix REL32 relocations with negative offsets.
2020-06-21 23:09:03 -04:00
remove-short-exec-branches-gpr-idx-mode.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
remove-short-exec-branches-mode-def.mir
AMDGPU: Don't run mode switches with exec 0
2020-06-02 13:47:48 -04:00
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
rename-independent-subregs.mir
[AMDGPU] Define 16 bit SGPR subregs
2020-04-16 10:31:39 -07:00
reorder-stores.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
reqd-work-group-size.ll
Enable `align <n>` to be used in the intrinsic definition.
2020-05-27 16:38:18 -04:00
reserve-vgpr-for-sgpr-spill.ll
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
ret.ll
AMDGPU/GlobalISel: Handle most function return types
2019-07-26 02:36:05 +00:00
ret_jump.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
returnaddress.ll
…
rewrite-out-arguments-address-space.ll
IR: print value numbers for unnamed function arguments
2019-08-03 14:28:34 +00:00
rewrite-out-arguments.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
rotl.i64.ll
…
rotl.ll
…
rotr.i64.ll
…
rotr.ll
…
rsq.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
rv7x0_count3.ll
…
s_add_co_pseudo_lowering.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
s_addk_i32.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
s_code_end.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
s_movk_i32.ll
…
s_mulk_i32.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
sad.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
saddo.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
salu-to-valu.ll
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
2020-06-24 00:39:41 +05:30
sampler-resource-id.ll
…
scalar-branch-missing-and-exec.ll
…
scalar-store-cache-flush.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
scalar_to_vector.ll
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
scalar_to_vector_v2x16.ll
…
sched-assert-dead-def-subreg-use-other-subreg.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sched-assert-onlydbg-value-empty-region.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sched-crash-dbg-value.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
schedule-barrier-fpmode.mir
AMDGPU: Add missing test for s_denorm_mode scheduling
2020-05-28 11:07:22 -04:00
schedule-barrier.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp.ll
…
schedule-kernel-arg-loads.ll
…
schedule-regpressure-limit-clustering.ll
[AMDGPU] Attempt to reschedule withou clustering
2020-01-27 10:27:16 -08:00
schedule-regpressure-limit.ll
…
schedule-regpressure-limit2.ll
…
schedule-regpressure-limit3.ll
…
schedule-regpressure.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
scheduler-handle-move-bundle.mir
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
scheduler-subrange-crash.ll
…
scratch-buffer.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
scratch-simple.ll
[CodeGen] Ensure callers of CreateStackTemporary use sensible alignments
2020-06-09 08:10:17 +01:00
sdiv.ll
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
sdiv64.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
sdivrem24.ll
…
sdivrem64.r600.ll
AMDGPU: Enable integer division bypass
2020-02-19 17:50:19 -05:00
sdwa-gfx9.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sdwa-op64-test.ll
…
sdwa-ops.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sdwa-peephole-instr-gfx10.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sdwa-peephole-instr.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sdwa-peephole.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
sdwa-preserve.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sdwa-scalar-ops.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sdwa-vop2-64bit.mir
…
select-constant-cttz.ll
[AMDGPU] Fix typos in performCtlz_CttzCombine()
2020-07-14 10:18:18 +01:00
select-fabs-fneg-extract-legacy.ll
…
select-fabs-fneg-extract.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
select-i1.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
select-opt.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
select-undef.ll
…
select-vectors.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
select.f16.ll
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal
2020-05-12 16:05:12 -07:00
select.ll
…
select64.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
selectcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
sendmsg-m0-hazard.mir
…
set-dx10.ll
…
set-gpr-idx-peephole.mir
AMDGPU: Don't run indexing mode switches with exec = 0
2020-06-02 13:47:48 -04:00
setcc-equivalent.ll
…
setcc-fneg-constant.ll
…
setcc-limit-load-shrink.ll
…
setcc-opt.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
setcc-sext.ll
…
setcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
setcc64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
seto.ll
…
setuo.ll
…
sext-divergence-driven-isel.ll
[AMDGPU] Enable SEXT divergence driven selection.
2020-03-17 17:30:11 +03:00
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sgpr-control-flow.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
sgpr-copy-duplicate-operand.ll
…
sgpr-copy.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
sgpr-spill-wrong-stack-id.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
sgpr-spill.mir
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
sgprcopies.ll
…
shader-addr64-nonuniform.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
…
shift-and-i128-ubfe.ll
…
shift-i64-opts.ll
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal
2020-05-12 16:05:12 -07:00
shift-i128.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
shift-select.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
shl-add-to-add-shl.ll
…
shl.ll
[AMDGPU] Remove unnecessary s_waitcnt between VMEM loads
2020-05-01 10:10:23 +01:00
shl.v2i16.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
shl_add.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
shl_add_constant.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
shl_add_ptr.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
shl_or.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
shrink-add-sub-constant.ll
AMDGPU: Don't use 16-bit FP inline constants in integer operands
2020-06-17 19:14:10 -04:00
shrink-carry.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
shrink-instructions-flags.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
shrink-vop3-carry-out.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
si-annotate-cf-noloop.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
si-annotate-cf-unreachable.ll
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
2019-06-13 23:47:36 +00:00
si-annotate-cf.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
si-annotate-cfg-loop-assert.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
si-annotatecfg-multiple-backedges.ll
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
2020-02-03 07:02:05 -08:00
si-fix-sgpr-copies.mir
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
si-i1-copies.mir
MachineSSAUpdater: insert IMPLICIT_DEF at top of basic block
2019-10-08 12:46:20 +00:00
si-if-lower-user-terminators.mir
AMDGPU: Fix SI_IF lowering when the save exec reg has terminator uses
2020-02-09 17:59:19 -05:00
si-instr-info-correct-implicit-operands.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
si-lower-control-flow-kill.ll
…
si-lower-control-flow-unreachable-block.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
si-lower-control-flow.mir
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
si-lower-i1-copies.mir
…
si-lower-sgpr-spills.mir
[AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass
2019-07-19 18:50:53 +00:00
si-scheduler.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
si-sgpr-spill.ll
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
si-spill-cf.ll
…
si-spill-sgpr-stack.ll
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
si-triv-disjoint-mem-access.ll
AMDGPU: Fix SMRD test in trivially disjoint mem access code
2020-03-05 17:14:01 +00:00
si-vector-hang.ll
…
sibling-call.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
sign_extend.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
simplify-libcalls.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
simplify-libcalls2.ll
[AMDGPU][NFC] Skip processing intrinsics that do not become real instructions
2020-06-09 03:45:33 +03:00
simplifydemandedbits-recursion.ll
…
sint_to_fp.f64.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
sint_to_fp.i64.ll
[AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32
2019-07-10 14:53:47 +00:00
sint_to_fp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
sitofp.f16.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
skip-branch-taildup-ret.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
skip-branch-trap.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
skip-if-dead.ll
[AMDGPU] Insert PS early exit at end of control flow
2020-07-03 14:04:34 +09:00
smed3.ll
…
smem-no-clause-coalesced.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
smem-war-hazard.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sminmax.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sminmax.v2i16.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
smrd-fold-offset.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
smrd-gfx10.ll
AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsic
2019-06-16 17:14:12 +00:00
smrd-vccz-bug.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
smrd.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
smrd_vmem_war.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
sopk-compares.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
speculative-execution-freecasts.ll
SpeculativeExecution: fixed ingoring free execution
2020-02-20 14:45:02 +03:00
spill-agpr.ll
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
spill-alloc-sgpr-init-bug.ll
…
spill-before-exec.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
spill-cfg-position.ll
…
spill-csr-frame-ptr-reg-copy.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
spill-empty-live-interval.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
spill-m0.ll
RegAllocFast: Record internal state based on register units
2020-06-03 16:51:46 -04:00
spill-offset-calculation.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
spill-scavenge-offset.ll
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
spill-special-sgpr.mir
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
spill-vgpr-to-agpr.ll
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
spill-wide-sgpr.ll
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
spill192.mir
AMDGPU: Fix spill/restore of 192-bit registers
2020-06-14 13:12:01 -04:00
spill_more_than_wavesize_csr_sgprs.ll
[AMDGPU] Spill more than wavesize CSR SGPRs
2020-07-01 07:40:47 +00:00
split-arg-dbg-value.ll
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
2020-06-17 12:41:03 -04:00
split-scalar-i64-add.ll
…
split-smrd.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
split-vector-memoperand-offsets.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
splitkit.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
sra.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sram-ecc-default.ll
…
srem.ll
…
srem64.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
srl.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sroa-before-unroll.ll
AMDGPU: Fix test in code directory
2020-06-01 13:26:51 -04:00
ssubo.ll
…
stack-pointer-offset-relative-frameindex.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
stack-realign-kernel.ll
AMDGPU: Assume f32 denormals are enabled by default
2020-04-02 17:17:12 -04:00
stack-realign.ll
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
stack-size-overflow.ll
…
stack-slot-color-sgpr-vgpr-spills.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
store-barrier.ll
…
store-global.ll
…
store-hi16.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
store-local.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
store-private.ll
…
store-v3i64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
store-vector-ptrs.ll
…
store-weird-sizes.ll
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
2020-06-24 00:39:41 +05:30
store_typed.ll
…
stress-calls.ll
…
strict_fadd.f16.ll
AMDGPU: Select strict_fadd
2020-06-04 17:49:00 -04:00
strict_fadd.f32.ll
AMDGPU: Select strict_fadd
2020-06-04 17:49:00 -04:00
strict_fadd.f64.ll
AMDGPU: Select strict_fadd
2020-06-04 17:49:00 -04:00
strict_fma.f16.ll
AMDGPU: Select strict_fma
2020-06-04 17:49:00 -04:00
strict_fma.f32.ll
AMDGPU: Select strict_fma
2020-06-04 17:49:00 -04:00
strict_fma.f64.ll
AMDGPU: Select strict_fma
2020-06-04 17:49:00 -04:00
strict_fmul.f16.ll
AMDGPU: Select strict_fmul
2020-06-04 17:49:00 -04:00
strict_fmul.f32.ll
AMDGPU: Select strict_fmul
2020-06-04 17:49:00 -04:00
strict_fmul.f64.ll
AMDGPU: Select strict_fmul
2020-06-04 17:49:00 -04:00
structurize.ll
…
structurize1.ll
…
sub-zext-cc-zext-cc.ll
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
2020-03-11 17:59:21 +00:00
sub.i16.ll
[AMDGPU] Fix bundle scheduling
2020-01-09 15:56:36 -08:00
sub.ll
…
sub.v2i16.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
sub_i1.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
subreg-coalescer-crash.ll
…
subreg-coalescer-undef-use.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
subreg-eliminate-dead.ll
…
subreg-intervals.mir
…
subreg-split-live-in-error.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
subreg-undef-def-with-other-subreg-defs.mir
[AMDGPU] Define AGPR subregs
2020-04-28 15:30:43 -07:00
subreg_interference.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
subvector-test.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
switch-default-block-unreachable.ll
[AMDGPU] Move LowerSwitch pass to CodeGenPrepare.
2020-07-11 16:33:38 +05:30
switch-unreachable.ll
[AMDGPU] add generated checks for some LIT tests
2020-03-03 11:47:05 +05:30
swizzle-export.ll
…
syncscopes.ll
…
tail-call-cgp.ll
…
tail-dup-bundle.mir
Process BUNDLE in tail duplication
2020-01-15 15:46:57 -08:00
tail-duplication-convergent.ll
AMDGPU: Add intrinsics for DS GWS semaphore instructions
2019-06-20 21:11:42 +00:00
target-cpu.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
tex-clause-antidep.ll
…
texture-input-merge.ll
…
transform-block-with-return-to-epilog.ll
[AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips.
2020-06-29 20:41:53 +05:30
trap.ll
…
trunc-bitcast-vector.ll
…
trunc-cmp-constant.ll
[AMDGPU] Fix CHECK lines
2020-04-03 10:07:21 +01:00
trunc-combine.ll
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
2019-12-17 18:54:27 +00:00
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll
…
trunc-store-i64.ll
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
2020-06-24 00:39:41 +05:30
trunc-store-vec-i16-to-i8.ll
[AMDGPU] Expand vector trunc stores from i16 to i8
2020-04-07 21:47:45 -07:00
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll
…
trunc.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
tti-unroll-prefs.ll
…
twoaddr-fma.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
twoaddr-mad.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
uaddo.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
udiv.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
udiv64.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
udivrem.ll
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
udivrem24.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
udivrem64.r600.ll
AMDGPU: Cleanup and generate 64-bit div tests
2020-01-20 17:19:39 -05:00
uint_to_fp.f64.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
uint_to_fp.i64.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
uint_to_fp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
uitofp.f16.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
umed3.ll
…
unaligned-load-store.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
undefined-physreg-sgpr-spill.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
undefined-subreg-liverange.ll
Regenerate subreg liverange tests. NFC.
2020-07-06 13:58:25 +01:00
unhandled-loop-condition-assertion.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
uniform-branch-intrinsic-cond.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
uniform-cfg.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
uniform-crash.ll
…
uniform-loop-inside-nonuniform.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
uniform-work-group-attribute-missing.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-nested-function-calls.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-prevent-attribute-propagation.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-propagate-attribute.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-recursion-test.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-test.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
unify-metadata.ll
…
unigine-liveness-crash.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
unknown-processor.ll
…
unpack-half.ll
…
unroll.ll
[AMDGPU] Enable runtime unroll for LDS
2020-02-27 12:59:35 -08:00
unsupported-calls.ll
AMDGPU: Don't error on calls to null or undef
2019-10-20 07:46:04 +00:00
unsupported-cc.ll
…
unsupported-image-a16.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
unsupported-image-g16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
update-phi.ll
[AMDGPU] Fix AMDGPUUnifyDivergentExitNodes
2020-03-18 16:49:30 +01:00
urem.ll
…
urem64.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
use-sgpr-multiple-times.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
usubo.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
v1i64-kernel-arg.ll
…
v1024.ll
[AMDGPU] Change register type for v32 vectors
2019-07-16 20:06:00 +00:00
v_cndmask.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
v_cvt_pk_u8_f32.ll
…
v_mac.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
v_mac_f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
v_madak_f16.ll
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal
2020-05-12 16:05:12 -07:00
v_swap_b32.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
valu-i1.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
vccz-corrupt-bug-workaround.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
vcmpx-exec-war-hazard.mir
[AMDGPU] more gfx1010 tests. NFC.
2019-06-12 18:44:11 +00:00
vcmpx-permlane-hazard.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
vector-alloca-addrspacecast.ll
…
vector-alloca-atomic.ll
…
vector-alloca-bitcast.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
vector-alloca-limits.ll
[AMDGPU] Limit promote alloca to vector with VGPR budget
2020-07-01 15:57:24 -07:00
vector-alloca.ll
…
vector-extract-insert.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
vector-legalizer-divergence.ll
…
vector_shuffle.packed.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
vectorize-buffer-fat-pointer.ll
…
vectorize-global-local.ll
…
vectorize-loads.ll
[AMDGPU] Disable sub-dword scralar loads IR widening
2020-04-10 08:20:49 -07:00
verify-sop.mir
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
vertex-fetch-encoding.ll
…
vgpr-descriptor-waterfall-loop-idom-update.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
vgpr-spill-emergency-stack-slot-compute.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
vgpr-spill-emergency-stack-slot.ll
[CodeGen] Ensure callers of CreateStackTemporary use sensible alignments
2020-06-09 08:10:17 +01:00
vgpr-tuple-allocation.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
vi-removed-intrinsics.ll
…
virtregrewrite-undef-identity-copy.mir
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
vmem-to-salu-hazard.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vmem-vcc-hazard.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
vop-shrink-frame-index.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vop-shrink-non-ssa.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vop-shrink.ll
…
vselect.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
vselect64.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll
[AMDGPU] Order pos exports before param exports
2020-05-12 23:02:23 +09:00
waitcnt-back-edge-loop.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
waitcnt-debug.mir
…
waitcnt-flat.ll
…
waitcnt-loop-irreducible.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
waitcnt-loop-single-basic-block.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
waitcnt-looptest.ll
…
waitcnt-no-redundant.mir
…
waitcnt-overflow.mir
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
waitcnt-permute.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
waitcnt-preexisting.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
waitcnt-skip-meta.mir
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
2020-06-17 12:41:03 -04:00
waitcnt-vmem-waw.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
waitcnt-vscnt.ll
[AMDGPU] Mark s_barrier as having side effects but not accessing memory.
2019-09-06 10:07:28 +00:00
waitcnt-vscnt.mir
[amdgpu] Fix scoreboard updating on `s_waitcnt_vscnt`.
2019-12-31 14:20:30 -05:00
waitcnt.mir
[AMDGPU] Fix wait counts in the presence of 16bit subregisters
2020-05-26 12:19:27 +03:00
wave32.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
wave_dispatch_regs.ll
…
widen-smrd-loads.ll
AMDGPU: Clear subreg when folding immediate copies
2020-07-01 13:59:13 -04:00
widen-vselect-and-mask.ll
…
widen_extending_scalar_loads.ll
Make IRBuilder automatically set alignment on load/store/alloca.
2020-04-13 13:43:14 -07:00
wqm.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
wqm.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
write-register-vgpr-into-sgpr.ll
…
write_register.ll
AMDGPU: Split test function
2020-01-12 22:44:51 -05:00
wrong-transalu-pos-fix.ll
…
wwm-reserved.ll
[AMDGPU] Add some missing -LABEL checks
2020-06-19 15:34:14 +01:00
xfail.r600.bitcast.ll
…
xnor.ll
…
xor.ll
…
xor3-i1-const.ll
…
xor3.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
xor_add.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
zero_extend.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
zext-i64-bit-operand.ll
…
zext-lid.ll
[AMDGPU] Packed thread ids in function call ABI
2019-06-28 01:52:13 +00:00
