llvm-project

History

Amara Emerson d5015edb37 Revert r351584: "GlobalISel: Verify g_zextload and g_sextload" This new assertion triggered on the AArch64 GlobalISel bots. Reverting while it's being investigated. llvm-svn: 351617		2019-01-19 00:36:11 +00:00
..
AArch64	Revert r351584: "GlobalISel: Verify g_zextload and g_sextload"	2019-01-19 00:36:11 +00:00
AMDGPU	AMDGPU: Fix tests using old number for constant address space	2018-09-10 02:54:25 +00:00
ARM	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Generic	[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL	2018-10-01 21:59:45 +00:00
Hexagon	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Mips	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
NVPTX	[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.	2018-01-10 00:56:48 +00:00
PowerPC	[Power9] Allow gpr callee saved spills in prologue to vectors registers	2018-11-09 16:36:24 +00:00
WebAssembly	[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)	2018-05-08 02:02:50 +00:00
X86	[mir] Serialize DILocation inline when not possible to use a metadata reference	2018-12-13 14:25:27 +00:00
README	…

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.