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llvm-project/llvm/test/CodeGen/MIR
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Ahmed Bougacha 5a59b24bdd [GlobalISel] Mark newly-created gvregs as having a bank. 
Also verify that we never try to set the size of a vreg associated
to a register class.

Report an error when we encounter that in MIR. Fix a testcase that
hit that error and had a size for no reason.

llvm-svn: 276012
 		2016-07-19 19:48:36 +00:00
..
AArch64 llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
AMDGPU llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
ARM llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
Generic llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
Hexagon [MIR] Print on the given output instead of stderr. 2016-07-13 20:36:03 +00:00
Lanai [MIR] Print on the given output instead of stderr. 2016-07-13 20:36:03 +00:00
Mips llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
NVPTX llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
PowerPC llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
X86 [GlobalISel] Mark newly-created gvregs as having a bank. 2016-07-19 19:48:36 +00:00