Matt Arsenault a1fe17c9ad AMDGPU: Change fdiv lowering based on !fpmath metadata ... If 2.5 ulp is acceptable, denormals are not required, and isn't a reciprocal which will already be handled, replace with a faster fdiv. Simplify the lowering tests by using per function subtarget features. llvm-svn: 276051		2016-07-19 23:16:53 +00:00
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AArch64	[AArch64] Properly validate the reciprocal estimation.	2016-07-19 22:31:11 +00:00
AMDGPU	AMDGPU: Change fdiv lowering based on !fpmath metadata	2016-07-19 23:16:53 +00:00
ARM	[ARM] Refactor Thumb2 Mul and Mla instr descs	2016-07-19 14:44:05 +00:00
BPF	[BPF] Remove exit-on-error from tests (PR27768, PR27769)	2016-05-30 08:28:34 +00:00
Generic	Move mempcpy_call.ll to X86 subdirectory	2016-07-13 18:28:45 +00:00
Hexagon	[Hexagon] Handle returning small structures by value	2016-07-18 17:30:41 +00:00
Inputs	…
Lanai	[lanai] Use peephole optimizer to generate more conditional ALU operations.	2016-07-07 23:36:04 +00:00
MIR	[GlobalISel] Mark newly-created gvregs as having a bank.	2016-07-19 19:48:36 +00:00
MSP430	…
Mips	RegScavenging: Add scavengeRegisterBackwards()	2016-07-19 22:37:09 +00:00
NVPTX	[NVPTX] Make sure we adjust alignment at all call sites	2016-07-18 21:58:48 +00:00
PowerPC	RegScavenging: Add scavengeRegisterBackwards()	2016-07-19 22:37:09 +00:00
SPARC	VirtRegMap: Replace some identity copies with KILL instructions.	2016-07-09 00:19:07 +00:00
SystemZ	RegScavenging: Add scavengeRegisterBackwards()	2016-07-19 22:37:09 +00:00
Thumb	RegScavenging: Add scavengeRegisterBackwards()	2016-07-19 22:37:09 +00:00
Thumb2	[Thumb] Reapply r272251 with a fix for PR28348 (mk 2)	2016-07-05 12:37:13 +00:00
WebAssembly	[WebAssembly] Emit type signatures for declared functions	2016-06-03 18:34:36 +00:00
WinEH	revert http://reviews.llvm.org/D21101	2016-06-30 17:52:24 +00:00
X86	[X86][AVX512] Added AVX512 subvector broadcast tests	2016-07-19 17:04:28 +00:00
XCore	IR: Introduce Module::global_objects().	2016-06-22 20:29:42 +00:00