forked from OSchip/llvm-project
504 lines
15 KiB
LLVM
504 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
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define i32 @fold_srem_positive_odd(i32 %x) nounwind {
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; RV32I-LABEL: fold_srem_positive_odd:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a1, zero, 95
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; RV32I-NEXT: call __modsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: fold_srem_positive_odd:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 706409
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; RV32IM-NEXT: addi a1, a1, 389
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; RV32IM-NEXT: mulh a1, a0, a1
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; RV32IM-NEXT: add a1, a1, a0
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; RV32IM-NEXT: srli a2, a1, 31
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; RV32IM-NEXT: srai a1, a1, 6
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; RV32IM-NEXT: add a1, a1, a2
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; RV32IM-NEXT: addi a2, zero, 95
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: sub a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: fold_srem_positive_odd:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: addi a1, zero, 95
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: fold_srem_positive_odd:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: sext.w a0, a0
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; RV64IM-NEXT: lui a1, 1045903
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; RV64IM-NEXT: addiw a1, a1, -733
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; RV64IM-NEXT: slli a1, a1, 15
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; RV64IM-NEXT: addi a1, a1, 1035
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -905
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -1767
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; RV64IM-NEXT: mulh a1, a0, a1
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; RV64IM-NEXT: add a1, a1, a0
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; RV64IM-NEXT: srli a2, a1, 63
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; RV64IM-NEXT: srai a1, a1, 6
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; RV64IM-NEXT: add a1, a1, a2
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; RV64IM-NEXT: addi a2, zero, 95
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: sub a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i32 %x, 95
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ret i32 %1
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}
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define i32 @fold_srem_positive_even(i32 %x) nounwind {
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; RV32I-LABEL: fold_srem_positive_even:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a1, zero, 1060
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; RV32I-NEXT: call __modsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: fold_srem_positive_even:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 253241
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; RV32IM-NEXT: addi a1, a1, -15
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; RV32IM-NEXT: mulh a1, a0, a1
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; RV32IM-NEXT: srli a2, a1, 31
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; RV32IM-NEXT: srai a1, a1, 8
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; RV32IM-NEXT: add a1, a1, a2
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; RV32IM-NEXT: addi a2, zero, 1060
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: sub a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: fold_srem_positive_even:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: addi a1, zero, 1060
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: fold_srem_positive_even:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: sext.w a0, a0
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; RV64IM-NEXT: lui a1, 506482
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; RV64IM-NEXT: addiw a1, a1, -31
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; RV64IM-NEXT: slli a1, a1, 13
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; RV64IM-NEXT: addi a1, a1, 711
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; RV64IM-NEXT: slli a1, a1, 19
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; RV64IM-NEXT: addi a1, a1, 1979
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; RV64IM-NEXT: mulh a1, a0, a1
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; RV64IM-NEXT: srli a2, a1, 63
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; RV64IM-NEXT: srai a1, a1, 9
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; RV64IM-NEXT: add a1, a1, a2
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; RV64IM-NEXT: addi a2, zero, 1060
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: sub a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i32 %x, 1060
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ret i32 %1
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}
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define i32 @fold_srem_negative_odd(i32 %x) nounwind {
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; RV32I-LABEL: fold_srem_negative_odd:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a1, zero, -723
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; RV32I-NEXT: call __modsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: fold_srem_negative_odd:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 677296
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; RV32IM-NEXT: addi a1, a1, -91
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; RV32IM-NEXT: mulh a1, a0, a1
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; RV32IM-NEXT: srli a2, a1, 31
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; RV32IM-NEXT: srai a1, a1, 8
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; RV32IM-NEXT: add a1, a1, a2
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; RV32IM-NEXT: addi a2, zero, -723
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: sub a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: fold_srem_negative_odd:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: addi a1, zero, -723
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: fold_srem_negative_odd:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: sext.w a0, a0
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; RV64IM-NEXT: lui a1, 4781
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; RV64IM-NEXT: addiw a1, a1, 2045
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; RV64IM-NEXT: slli a1, a1, 13
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; RV64IM-NEXT: addi a1, a1, 1371
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; RV64IM-NEXT: slli a1, a1, 13
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; RV64IM-NEXT: addi a1, a1, -11
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -1355
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; RV64IM-NEXT: mulh a1, a0, a1
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; RV64IM-NEXT: sub a1, a1, a0
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; RV64IM-NEXT: srli a2, a1, 63
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; RV64IM-NEXT: srai a1, a1, 9
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; RV64IM-NEXT: add a1, a1, a2
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; RV64IM-NEXT: addi a2, zero, -723
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: sub a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i32 %x, -723
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ret i32 %1
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}
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define i32 @fold_srem_negative_even(i32 %x) nounwind {
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; RV32I-LABEL: fold_srem_negative_even:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a1, 1048570
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; RV32I-NEXT: addi a1, a1, 1595
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; RV32I-NEXT: call __modsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: fold_srem_negative_even:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 1036895
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; RV32IM-NEXT: addi a1, a1, 999
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; RV32IM-NEXT: mulh a1, a0, a1
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; RV32IM-NEXT: srli a2, a1, 31
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; RV32IM-NEXT: srai a1, a1, 8
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; RV32IM-NEXT: add a1, a1, a2
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; RV32IM-NEXT: lui a2, 1048570
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; RV32IM-NEXT: addi a2, a2, 1595
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: sub a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: fold_srem_negative_even:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: lui a1, 1048570
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; RV64I-NEXT: addiw a1, a1, 1595
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: fold_srem_negative_even:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: sext.w a0, a0
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; RV64IM-NEXT: lui a1, 1036895
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; RV64IM-NEXT: addiw a1, a1, 999
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, 11
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -523
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -481
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; RV64IM-NEXT: mulh a1, a0, a1
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; RV64IM-NEXT: srli a2, a1, 63
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; RV64IM-NEXT: srai a1, a1, 12
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; RV64IM-NEXT: add a1, a1, a2
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; RV64IM-NEXT: lui a2, 1048570
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; RV64IM-NEXT: addiw a2, a2, 1595
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: sub a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i32 %x, -22981
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ret i32 %1
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}
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; Don't fold if we can combine srem with sdiv.
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define i32 @combine_srem_sdiv(i32 %x) nounwind {
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; RV32I-LABEL: combine_srem_sdiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: sw s1, 4(sp)
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; RV32I-NEXT: mv s0, a0
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; RV32I-NEXT: addi a1, zero, 95
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; RV32I-NEXT: call __modsi3
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; RV32I-NEXT: mv s1, a0
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; RV32I-NEXT: addi a1, zero, 95
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; RV32I-NEXT: mv a0, s0
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; RV32I-NEXT: call __divsi3
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; RV32I-NEXT: add a0, s1, a0
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; RV32I-NEXT: lw s1, 4(sp)
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: combine_srem_sdiv:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 706409
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; RV32IM-NEXT: addi a1, a1, 389
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; RV32IM-NEXT: mulh a1, a0, a1
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; RV32IM-NEXT: add a1, a1, a0
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; RV32IM-NEXT: srli a2, a1, 31
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; RV32IM-NEXT: srai a1, a1, 6
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; RV32IM-NEXT: add a1, a1, a2
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; RV32IM-NEXT: addi a2, zero, 95
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; RV32IM-NEXT: mul a2, a1, a2
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; RV32IM-NEXT: sub a0, a0, a2
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: combine_srem_sdiv:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -32
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; RV64I-NEXT: sd ra, 24(sp)
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; RV64I-NEXT: sd s0, 16(sp)
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; RV64I-NEXT: sd s1, 8(sp)
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; RV64I-NEXT: sext.w s0, a0
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; RV64I-NEXT: addi a1, zero, 95
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; RV64I-NEXT: mv a0, s0
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: mv s1, a0
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; RV64I-NEXT: addi a1, zero, 95
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; RV64I-NEXT: mv a0, s0
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; RV64I-NEXT: call __divdi3
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; RV64I-NEXT: addw a0, s1, a0
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; RV64I-NEXT: ld s1, 8(sp)
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; RV64I-NEXT: ld s0, 16(sp)
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; RV64I-NEXT: ld ra, 24(sp)
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; RV64I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: combine_srem_sdiv:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: sext.w a1, a0
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; RV64IM-NEXT: lui a2, 1045903
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; RV64IM-NEXT: addiw a2, a2, -733
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; RV64IM-NEXT: slli a2, a2, 15
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; RV64IM-NEXT: addi a2, a2, 1035
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; RV64IM-NEXT: slli a2, a2, 12
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; RV64IM-NEXT: addi a2, a2, -905
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; RV64IM-NEXT: slli a2, a2, 12
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; RV64IM-NEXT: addi a2, a2, -1767
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; RV64IM-NEXT: mulh a2, a1, a2
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; RV64IM-NEXT: add a1, a2, a1
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; RV64IM-NEXT: srli a2, a1, 63
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; RV64IM-NEXT: srai a1, a1, 6
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; RV64IM-NEXT: add a1, a1, a2
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; RV64IM-NEXT: addi a2, zero, 95
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; RV64IM-NEXT: mul a2, a1, a2
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; RV64IM-NEXT: sub a0, a0, a2
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; RV64IM-NEXT: addw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i32 %x, 95
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%2 = sdiv i32 %x, 95
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%3 = add i32 %1, %2
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ret i32 %3
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}
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; Don't fold for divisors that are a power of two.
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define i32 @dont_fold_srem_power_of_two(i32 %x) nounwind {
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; RV32I-LABEL: dont_fold_srem_power_of_two:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: srli a1, a1, 26
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; RV32I-NEXT: add a1, a0, a1
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; RV32I-NEXT: andi a1, a1, -64
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: dont_fold_srem_power_of_two:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: srai a1, a0, 31
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; RV32IM-NEXT: srli a1, a1, 26
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; RV32IM-NEXT: add a1, a0, a1
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; RV32IM-NEXT: andi a1, a1, -64
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; RV32IM-NEXT: sub a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: dont_fold_srem_power_of_two:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a1, a0
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; RV64I-NEXT: srli a1, a1, 57
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; RV64I-NEXT: andi a1, a1, 63
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; RV64I-NEXT: add a1, a0, a1
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: slli a2, a2, 32
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; RV64I-NEXT: addi a2, a2, -64
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: dont_fold_srem_power_of_two:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: sext.w a1, a0
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; RV64IM-NEXT: srli a1, a1, 57
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; RV64IM-NEXT: andi a1, a1, 63
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; RV64IM-NEXT: add a1, a0, a1
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; RV64IM-NEXT: addi a2, zero, 1
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; RV64IM-NEXT: slli a2, a2, 32
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; RV64IM-NEXT: addi a2, a2, -64
|
|
; RV64IM-NEXT: and a1, a1, a2
|
|
; RV64IM-NEXT: subw a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
%1 = srem i32 %x, 64
|
|
ret i32 %1
|
|
}
|
|
|
|
; Don't fold if the divisor is one.
|
|
define i32 @dont_fold_srem_one(i32 %x) nounwind {
|
|
; CHECK-LABEL: dont_fold_srem_one:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: mv a0, zero
|
|
; CHECK-NEXT: ret
|
|
%1 = srem i32 %x, 1
|
|
ret i32 %1
|
|
}
|
|
|
|
; Don't fold if the divisor is 2^31.
|
|
define i32 @dont_fold_srem_i32_smax(i32 %x) nounwind {
|
|
; RV32I-LABEL: dont_fold_srem_i32_smax:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: srai a1, a0, 31
|
|
; RV32I-NEXT: srli a1, a1, 1
|
|
; RV32I-NEXT: add a1, a0, a1
|
|
; RV32I-NEXT: lui a2, 524288
|
|
; RV32I-NEXT: and a1, a1, a2
|
|
; RV32I-NEXT: add a0, a0, a1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IM-LABEL: dont_fold_srem_i32_smax:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: srai a1, a0, 31
|
|
; RV32IM-NEXT: srli a1, a1, 1
|
|
; RV32IM-NEXT: add a1, a0, a1
|
|
; RV32IM-NEXT: lui a2, 524288
|
|
; RV32IM-NEXT: and a1, a1, a2
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: dont_fold_srem_i32_smax:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sext.w a1, a0
|
|
; RV64I-NEXT: srli a1, a1, 32
|
|
; RV64I-NEXT: lui a2, 524288
|
|
; RV64I-NEXT: addiw a2, a2, -1
|
|
; RV64I-NEXT: and a1, a1, a2
|
|
; RV64I-NEXT: add a1, a0, a1
|
|
; RV64I-NEXT: addi a2, zero, 1
|
|
; RV64I-NEXT: slli a2, a2, 31
|
|
; RV64I-NEXT: and a1, a1, a2
|
|
; RV64I-NEXT: addw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: dont_fold_srem_i32_smax:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: sext.w a1, a0
|
|
; RV64IM-NEXT: srli a1, a1, 32
|
|
; RV64IM-NEXT: lui a2, 524288
|
|
; RV64IM-NEXT: addiw a2, a2, -1
|
|
; RV64IM-NEXT: and a1, a1, a2
|
|
; RV64IM-NEXT: add a1, a0, a1
|
|
; RV64IM-NEXT: addi a2, zero, 1
|
|
; RV64IM-NEXT: slli a2, a2, 31
|
|
; RV64IM-NEXT: and a1, a1, a2
|
|
; RV64IM-NEXT: addw a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
%1 = srem i32 %x, 2147483648
|
|
ret i32 %1
|
|
}
|
|
|
|
; Don't fold i64 srem
|
|
define i64 @dont_fold_srem_i64(i64 %x) nounwind {
|
|
; RV32I-LABEL: dont_fold_srem_i64:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: addi a2, zero, 98
|
|
; RV32I-NEXT: mv a3, zero
|
|
; RV32I-NEXT: call __moddi3
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IM-LABEL: dont_fold_srem_i64:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: addi sp, sp, -16
|
|
; RV32IM-NEXT: sw ra, 12(sp)
|
|
; RV32IM-NEXT: addi a2, zero, 98
|
|
; RV32IM-NEXT: mv a3, zero
|
|
; RV32IM-NEXT: call __moddi3
|
|
; RV32IM-NEXT: lw ra, 12(sp)
|
|
; RV32IM-NEXT: addi sp, sp, 16
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: dont_fold_srem_i64:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: addi a1, zero, 98
|
|
; RV64I-NEXT: call __moddi3
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: dont_fold_srem_i64:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: lui a1, 2675
|
|
; RV64IM-NEXT: addiw a1, a1, -251
|
|
; RV64IM-NEXT: slli a1, a1, 13
|
|
; RV64IM-NEXT: addi a1, a1, 1839
|
|
; RV64IM-NEXT: slli a1, a1, 13
|
|
; RV64IM-NEXT: addi a1, a1, 167
|
|
; RV64IM-NEXT: slli a1, a1, 13
|
|
; RV64IM-NEXT: addi a1, a1, 1505
|
|
; RV64IM-NEXT: mulh a1, a0, a1
|
|
; RV64IM-NEXT: srli a2, a1, 63
|
|
; RV64IM-NEXT: srai a1, a1, 5
|
|
; RV64IM-NEXT: add a1, a1, a2
|
|
; RV64IM-NEXT: addi a2, zero, 98
|
|
; RV64IM-NEXT: mul a1, a1, a2
|
|
; RV64IM-NEXT: sub a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
%1 = srem i64 %x, 98
|
|
ret i64 %1
|
|
}
|