forked from OSchip/llvm-project
246 lines
7.9 KiB
LLVM
246 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 < %s | FileCheck -check-prefix=RV32 %s
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; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64 %s
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; RUN: llc -mtriple=riscv32 -frame-pointer=all -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32-WITHFP %s
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; RUN: llc -mtriple=riscv64 -frame-pointer=all -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64-WITHFP %s
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define void @trivial() {
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; RV32-LABEL: trivial:
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; RV32: # %bb.0:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: trivial:
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; RV64: # %bb.0:
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; RV64-NEXT: ret
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;
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; RV32-WITHFP-LABEL: trivial:
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; RV32-WITHFP: # %bb.0:
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; RV32-WITHFP-NEXT: addi sp, sp, -16
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; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
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; RV32-WITHFP-NEXT: sw ra, 12(sp)
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; RV32-WITHFP-NEXT: sw s0, 8(sp)
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; RV32-WITHFP-NEXT: .cfi_offset ra, -4
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; RV32-WITHFP-NEXT: .cfi_offset s0, -8
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; RV32-WITHFP-NEXT: addi s0, sp, 16
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; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV32-WITHFP-NEXT: lw s0, 8(sp)
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; RV32-WITHFP-NEXT: lw ra, 12(sp)
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; RV32-WITHFP-NEXT: addi sp, sp, 16
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; RV32-WITHFP-NEXT: ret
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;
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; RV64-WITHFP-LABEL: trivial:
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; RV64-WITHFP: # %bb.0:
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; RV64-WITHFP-NEXT: addi sp, sp, -16
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; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
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; RV64-WITHFP-NEXT: sd ra, 8(sp)
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; RV64-WITHFP-NEXT: sd s0, 0(sp)
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; RV64-WITHFP-NEXT: .cfi_offset ra, -8
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; RV64-WITHFP-NEXT: .cfi_offset s0, -16
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; RV64-WITHFP-NEXT: addi s0, sp, 16
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; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV64-WITHFP-NEXT: ld s0, 0(sp)
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; RV64-WITHFP-NEXT: ld ra, 8(sp)
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; RV64-WITHFP-NEXT: addi sp, sp, 16
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; RV64-WITHFP-NEXT: ret
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ret void
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}
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define void @stack_alloc(i32 signext %size) {
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; RV32-LABEL: stack_alloc:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp)
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; RV32-NEXT: sw s0, 8(sp)
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: addi s0, sp, 16
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; RV32-NEXT: .cfi_def_cfa s0, 0
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; RV32-NEXT: addi a0, a0, 15
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; RV32-NEXT: andi a0, a0, -16
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; RV32-NEXT: sub a0, sp, a0
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; RV32-NEXT: mv sp, a0
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; RV32-NEXT: call callee_with_args
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; RV32-NEXT: addi sp, s0, -16
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; RV32-NEXT: lw s0, 8(sp)
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: stack_alloc:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: sd ra, 8(sp)
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; RV64-NEXT: sd s0, 0(sp)
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: addi s0, sp, 16
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; RV64-NEXT: .cfi_def_cfa s0, 0
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; RV64-NEXT: slli a0, a0, 32
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; RV64-NEXT: srli a0, a0, 32
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; RV64-NEXT: addi a0, a0, 15
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; RV64-NEXT: addi a1, zero, 1
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; RV64-NEXT: slli a1, a1, 33
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; RV64-NEXT: addi a1, a1, -16
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; RV64-NEXT: and a0, a0, a1
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; RV64-NEXT: sub a0, sp, a0
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; RV64-NEXT: mv sp, a0
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; RV64-NEXT: call callee_with_args
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; RV64-NEXT: addi sp, s0, -16
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; RV64-NEXT: ld s0, 0(sp)
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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;
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; RV32-WITHFP-LABEL: stack_alloc:
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; RV32-WITHFP: # %bb.0: # %entry
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; RV32-WITHFP-NEXT: addi sp, sp, -16
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; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
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; RV32-WITHFP-NEXT: sw ra, 12(sp)
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; RV32-WITHFP-NEXT: sw s0, 8(sp)
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; RV32-WITHFP-NEXT: .cfi_offset ra, -4
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; RV32-WITHFP-NEXT: .cfi_offset s0, -8
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; RV32-WITHFP-NEXT: addi s0, sp, 16
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; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV32-WITHFP-NEXT: addi a0, a0, 15
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; RV32-WITHFP-NEXT: andi a0, a0, -16
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; RV32-WITHFP-NEXT: sub a0, sp, a0
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; RV32-WITHFP-NEXT: mv sp, a0
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; RV32-WITHFP-NEXT: call callee_with_args
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; RV32-WITHFP-NEXT: addi sp, s0, -16
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; RV32-WITHFP-NEXT: lw s0, 8(sp)
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; RV32-WITHFP-NEXT: lw ra, 12(sp)
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; RV32-WITHFP-NEXT: addi sp, sp, 16
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; RV32-WITHFP-NEXT: ret
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;
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; RV64-WITHFP-LABEL: stack_alloc:
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; RV64-WITHFP: # %bb.0: # %entry
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; RV64-WITHFP-NEXT: addi sp, sp, -16
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; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
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; RV64-WITHFP-NEXT: sd ra, 8(sp)
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; RV64-WITHFP-NEXT: sd s0, 0(sp)
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; RV64-WITHFP-NEXT: .cfi_offset ra, -8
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; RV64-WITHFP-NEXT: .cfi_offset s0, -16
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; RV64-WITHFP-NEXT: addi s0, sp, 16
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; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV64-WITHFP-NEXT: slli a0, a0, 32
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; RV64-WITHFP-NEXT: srli a0, a0, 32
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; RV64-WITHFP-NEXT: addi a0, a0, 15
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; RV64-WITHFP-NEXT: addi a1, zero, 1
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; RV64-WITHFP-NEXT: slli a1, a1, 33
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; RV64-WITHFP-NEXT: addi a1, a1, -16
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; RV64-WITHFP-NEXT: and a0, a0, a1
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; RV64-WITHFP-NEXT: sub a0, sp, a0
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; RV64-WITHFP-NEXT: mv sp, a0
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; RV64-WITHFP-NEXT: call callee_with_args
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; RV64-WITHFP-NEXT: addi sp, s0, -16
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; RV64-WITHFP-NEXT: ld s0, 0(sp)
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; RV64-WITHFP-NEXT: ld ra, 8(sp)
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; RV64-WITHFP-NEXT: addi sp, sp, 16
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; RV64-WITHFP-NEXT: ret
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entry:
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%0 = alloca i8, i32 %size, align 16
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call void @callee_with_args(i8* nonnull %0)
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ret void
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}
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define void @branch_and_tail_call(i1 %a) {
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; RV32-LABEL: branch_and_tail_call:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp)
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: beqz a0, .LBB2_2
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; RV32-NEXT: # %bb.1: # %blue_pill
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: tail callee1
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; RV32-NEXT: .LBB2_2: # %red_pill
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; RV32-NEXT: call callee2
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: branch_and_tail_call:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: sd ra, 8(sp)
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: andi a0, a0, 1
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; RV64-NEXT: beqz a0, .LBB2_2
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; RV64-NEXT: # %bb.1: # %blue_pill
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: tail callee1
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; RV64-NEXT: .LBB2_2: # %red_pill
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; RV64-NEXT: call callee2
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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;
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; RV32-WITHFP-LABEL: branch_and_tail_call:
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; RV32-WITHFP: # %bb.0:
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; RV32-WITHFP-NEXT: addi sp, sp, -16
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; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
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; RV32-WITHFP-NEXT: sw ra, 12(sp)
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; RV32-WITHFP-NEXT: sw s0, 8(sp)
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; RV32-WITHFP-NEXT: .cfi_offset ra, -4
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; RV32-WITHFP-NEXT: .cfi_offset s0, -8
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; RV32-WITHFP-NEXT: addi s0, sp, 16
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; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV32-WITHFP-NEXT: andi a0, a0, 1
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; RV32-WITHFP-NEXT: beqz a0, .LBB2_2
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; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill
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; RV32-WITHFP-NEXT: lw s0, 8(sp)
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; RV32-WITHFP-NEXT: lw ra, 12(sp)
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; RV32-WITHFP-NEXT: addi sp, sp, 16
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; RV32-WITHFP-NEXT: tail callee1
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; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill
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; RV32-WITHFP-NEXT: call callee2
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; RV32-WITHFP-NEXT: lw s0, 8(sp)
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; RV32-WITHFP-NEXT: lw ra, 12(sp)
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; RV32-WITHFP-NEXT: addi sp, sp, 16
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; RV32-WITHFP-NEXT: ret
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;
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; RV64-WITHFP-LABEL: branch_and_tail_call:
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; RV64-WITHFP: # %bb.0:
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; RV64-WITHFP-NEXT: addi sp, sp, -16
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; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
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; RV64-WITHFP-NEXT: sd ra, 8(sp)
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; RV64-WITHFP-NEXT: sd s0, 0(sp)
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; RV64-WITHFP-NEXT: .cfi_offset ra, -8
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; RV64-WITHFP-NEXT: .cfi_offset s0, -16
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; RV64-WITHFP-NEXT: addi s0, sp, 16
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; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV64-WITHFP-NEXT: andi a0, a0, 1
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; RV64-WITHFP-NEXT: beqz a0, .LBB2_2
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; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill
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; RV64-WITHFP-NEXT: ld s0, 0(sp)
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; RV64-WITHFP-NEXT: ld ra, 8(sp)
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; RV64-WITHFP-NEXT: addi sp, sp, 16
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; RV64-WITHFP-NEXT: tail callee1
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; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill
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; RV64-WITHFP-NEXT: call callee2
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; RV64-WITHFP-NEXT: ld s0, 0(sp)
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; RV64-WITHFP-NEXT: ld ra, 8(sp)
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; RV64-WITHFP-NEXT: addi sp, sp, 16
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; RV64-WITHFP-NEXT: ret
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br i1 %a, label %blue_pill, label %red_pill
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blue_pill:
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tail call void @callee1()
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ret void
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red_pill:
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call void @callee2()
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ret void
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}
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declare void @callee1()
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declare void @callee2()
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declare void @callee_with_args(i8*)
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