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llvm-project/llvm/test/CodeGen/RISCV
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Craig Topper 4252f7773a [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets. 
X86 was already specially marking fma as commutable which allowed
tablegen to autogenerate commuted patterns. This moves it to the target
independent definition and fix up the targets to remove now
unneeded patterns.

Unfortunately, the tests change because the commuted version of
the patterns are generating operands in a different than the
explicit patterns.

Differential Revision: https://reviews.llvm.org/D91842
 		2020-11-23 10:09:20 -08:00
..
GlobalISel [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
intrinsics [RISCV] Lower llvm.trap and llvm.debugtrap 2019-10-28 09:54:33 +00:00
add-before-shl.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
add-imm.ll [RISCV] optimize addition with a pair of (addi imm) 2020-07-07 18:57:28 -07:00
addc-adde-sube-subc.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
addcarry.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
addimm-mulimm.ll [RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation 2020-07-10 18:33:12 -07:00
align.ll
…
alloca.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
alu8.ll
…
alu16.ll
…
alu32.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
alu64.ll Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. 2019-12-05 14:32:11 +08:00
analyze-branch.ll
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arith-with-overflow.ll [TargetLowering] Simplify expansion of S{ADD,SUB}O 2019-09-30 07:58:50 +00:00
atomic-cmpxchg-flag.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
atomic-cmpxchg.ll [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG 2020-04-01 15:51:26 +01:00
atomic-fence.ll
…
atomic-load-store.ll
…
atomic-rmw.ll [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move 2020-08-27 10:32:22 +01:00
attributes.ll [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
bare-select.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
blockaddress.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
branch-relaxation.ll [RISCV] Indirect branch generation in position independent code 2020-08-17 13:09:26 +01:00
branch.ll Revert "[BPI] Improve static heuristics for integer comparisons" 2020-08-17 20:44:33 +02:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
byval.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
callee-saved-fpr32s.ll [RISCV] Fold ADDIs into load/stores with nonzero offsets 2020-07-06 17:32:57 +01:00
callee-saved-fpr64s.ll [RISCV] Fold ADDIs into load/stores with nonzero offsets 2020-07-06 17:32:57 +01:00
callee-saved-gprs.ll [RISCV] Fold ADDIs into load/stores with nonzero offsets 2020-07-06 17:32:57 +01:00
calling-conv-ilp32-ilp32f-common.ll [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move 2020-08-27 10:32:22 +01:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
calling-conv-ilp32.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32d.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
calling-conv-lp64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-rv32f-ilp32.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-sext-zext.ll
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calls.ll [RISCV] Lower calls through PLT 2019-06-18 14:29:45 +00:00
cmp-bool.ll [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1) 2020-07-15 07:34:22 +00:00
codemodel-lowering.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
compress-float.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
compress-inline-asm.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
compress.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
copy-frameindex.mir [RISCV] Only return DestSourcePair from isCopyInstrImpl for registers 2020-11-03 03:55:47 +00:00
copysign-casts.ll [LegalizeTypes][RISCV] Soften FCOPYSIGN operand 2019-11-26 15:22:55 +00:00
disable-tail-calls.ll
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disjoint.ll [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook 2019-11-05 09:39:06 +00:00
div.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-arith.ll [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets. 2020-11-23 10:09:20 -08:00
double-bitmanip-dagcombines.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-br-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-calling-conv.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-frem.ll
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double-imm.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
double-intrinsics.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-isnan.ll [RISCV] Add patterns for checking isnan 2020-05-02 15:01:04 +01:00
double-mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-previous-failure.ll [RISCV] Implement Hooks to avoid chaining SELECT 2020-07-01 11:56:31 +01:00
double-select-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-stack-spill-restore.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
dwarf-eh.ll [RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll 2019-07-17 14:04:48 +00:00
exception-pointer-register.ll [RISCV] Fix wrong CFI directives 2019-11-14 18:29:50 +00:00
fastcc-float.ll [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
fastcc-int.ll [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
fixups-diff.ll [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
fixups-relax-diff.ll [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
float-arith.ll [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets. 2020-11-23 10:09:20 -08:00
float-bit-preserving-dagcombines.ll
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float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w 2020-03-20 09:42:24 +00:00
float-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-frem.ll
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float-imm.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
float-intrinsics.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-isnan.ll [RISCV] Add patterns for checking isnan 2020-05-02 15:01:04 +01:00
float-mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-select-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
flt-rounds.ll
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fold-addi-loadstore.ll [RISCV] Fold ADDIs into load/stores with nonzero offsets 2020-07-06 17:32:57 +01:00
fp-imm.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
fp16-promote.ll [RISCV] Add support for half-precision floats 2019-10-25 14:02:02 +01:00
fp128.ll [RISCV] Fold ADDIs into load/stores with nonzero offsets 2020-07-06 17:32:57 +01:00
frame-info.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
frame.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
frameaddr-returnaddr.ll
…
get-register-invalid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
get-register-noreserve.ll [RISCV] Implement the TargetLowering::getRegisterByName hook 2019-11-04 11:23:54 +00:00
get-register-reserve.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
get-setcc-result-type.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
hoist-global-addr-base.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
i32-icmp.ll [RISCV] Optimize seteq/setne pattern expansions for better code size 2020-02-11 22:45:15 +08:00
imm-cse.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
imm.ll [RISCV][NFC] Add more tests for 32-bit constant materialization 2020-10-22 11:36:34 +01:00
indirectbr.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
init-array.ll
…
inline-asm-abi-names.ll [MC][RISCV] Set UseIntegratedAssembler to true 2020-07-12 21:04:48 -07:00
inline-asm-clobbers.ll [RISCV] Add support for lowering floating point inlineasm clobbers 2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-d-constraint-f.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
inline-asm-f-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-f-constraint-f.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll Emit diagnostic if an inline asm constraint requires an immediate 2019-08-03 05:52:47 +00:00
inline-asm.ll [MC][RISCV] Set UseIntegratedAssembler to true 2020-07-12 21:04:48 -07:00
interrupt-attr-args-error.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr-callee.ll [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler 2020-02-15 09:14:04 +08:00
interrupt-attr-invalid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr-nocall.ll [RISCV] Fold ADDIs into load/stores with nonzero offsets 2020-07-06 17:32:57 +01:00
interrupt-attr-ret-error.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr.ll Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351 2019-12-24 15:57:33 -08:00
jumptable.ll
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large-stack.ll [MC][RISCV] Set UseIntegratedAssembler to true 2020-07-12 21:04:48 -07:00
legalize-fneg.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
lit.local.cfg
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lsr-legaladdimm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
machineoutliner.mir [RISCV] Enable the machine outliner for RISC-V 2019-12-19 16:41:53 +00:00
mattr-invalid-combination.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mem64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mir-target-flags.ll Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" 2020-07-14 11:15:01 +01:00
module-target-abi.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
module-target-abi2.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
mul.ll [RISCV] Optimize multiplication by constant 2020-07-07 18:50:24 -07:00
musttail-call.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
neg-abs.ll [RISCV] Extend 32-bit test coverage of neg-abs tests for D91120 2020-11-19 13:59:18 +00:00
nomerge.ll Add NoMerge MIFlag to avoid MIR branch folding 2020-05-29 12:31:06 -07:00
option-nopic.ll [RISCV][AsmParser] Implement .option (no)pic 2020-04-17 12:08:30 +00:00
option-norelax.ll [llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:` 2020-03-05 18:05:28 -08:00
option-norvc.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
option-pic.ll [RISCV][AsmParser] Implement .option (no)pic 2020-04-17 12:08:30 +00:00
option-relax.ll [llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:` 2020-03-05 18:05:28 -08:00
option-rvc.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
pic-models.ll Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" 2020-07-14 11:15:01 +01:00
pr40333.ll
…
prefetch.ll
…
readcyclecounter.ll [RISCV] Support @llvm.readcyclecounter() Intrinsic 2019-07-05 12:35:21 +00:00
rem.ll
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remat.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
reserved-reg-errors.ll [RISCV] Add support for -ffixed-xX flags 2019-10-22 21:25:01 +01:00
reserved-regs.ll [RISCV] Add support for -ffixed-xX flags 2019-10-22 21:25:01 +01:00
rotl-rotr.ll
…
rv32Zbb.ll [RISCV] Make ctlz/cttz cheap to speculatively execute so CodeGenPrepare won't insert a zero check. 2020-11-09 10:13:45 -08:00
rv32Zbbp.ll [RISCV] Add isel patterns for using PACK for zext.h and zext.w. 2020-11-09 10:13:45 -08:00
rv32Zbp.ll [RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb. 2020-11-20 10:25:47 -08:00
rv32Zbs.ll [RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift amount isn't masked. 2020-11-09 09:55:26 -08:00
rv32Zbt.ll [RISCV] Add an ANDI to shift amount of FSL/FSR instructions 2020-11-12 07:33:40 -08:00
rv32e.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
rv32i-rv64i-float-double.ll [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall 2019-08-28 23:40:37 +00:00
rv64-large-stack.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
rv64Zbb.ll [RISCV] When matching SROIW, check all 64 bits of the OR mask 2020-11-16 10:08:15 -08:00
rv64Zbbp.ll [RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb. 2020-11-20 10:25:47 -08:00
rv64Zbp.ll [RISCV] Custom type legalize i32 bswap/bitreverse to GREVIW on RV64 with Zbp extension 2020-11-20 10:41:01 -08:00
rv64Zbs.ll [RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift amount isn't masked. 2020-11-09 09:55:26 -08:00
rv64Zbt.ll [RISCV] Add test cases for fsrw/fslw that don't sign extend the result. NFC 2020-11-13 23:31:16 -08:00
rv64d-double-convert.ll
…
rv64f-float-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64i-complex-float.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64i-demanded-bits.ll [RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW 2020-10-29 14:52:53 -07:00
rv64i-double-softfloat.ll [RISCV] Use the 'si' lib call for (double (fp_to_sint/uint i32 X)) when F extension is enabled. 2020-11-05 10:46:45 -08:00
rv64i-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64i-single-softfloat.ll Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" 2020-11-04 19:58:11 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64m-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64m-w-insts-legalization.ll Revert "[BPI] Improve static heuristics for integer comparisons" 2020-08-17 20:44:33 +02:00
saverestore.ll [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
sdata-limit-0.ll
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sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll [RISCV] Implement Hooks to avoid chaining SELECT 2020-07-01 11:56:31 +01:00
select-cc.ll
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select-const.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
select-optimize-multiple.ll [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot 2020-11-18 19:20:03 -08:00
select-optimize-multiple.mir [MachineVerifier] Verify that a DBG_VALUE has a debug location 2020-05-28 13:53:40 -07:00
select-or.ll [RISCV] Implement Hooks to avoid chaining SELECT 2020-07-01 11:56:31 +01:00
setcc-logic.ll [RISCV] Optimize seteq/setne pattern expansions for better code size 2020-02-11 22:45:15 +08:00
sext-zext-trunc.ll [DAGCombiner] Precommit Sext Tests for D91589 2020-11-18 15:56:16 +00:00
shadowcallstack.ll [RISCV] Support Shadow Call Stack 2020-09-17 16:02:35 -07:00
shift-masked-shamt.ll
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shifts.ll Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. 2019-12-05 14:32:11 +08:00
shrinkwrap.ll [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
split-offsets.ll [RISCV] Fix wrong CFI directives 2019-11-14 18:29:50 +00:00
split-sp-adjust.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
srem-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
srem-vector-lkk.ll [RISCV] srem-vector-lkk.ll - remove unused check prefix 2020-11-11 18:38:23 +00:00
stack-realignment-with-variable-sized-objects.ll [RISCV] Handle variable sized objects with the stack need to be realigned 2019-11-16 12:39:53 +08:00
stack-realignment.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
stack-store-check.ll [RISCV] Fix isStoreToStackSlot 2020-07-14 12:36:42 +00:00
subtarget-features-std-ext.ll [RISCV] Support ABI checking with per function target-features 2020-01-22 08:12:28 -08:00
tail-calls.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
target-abi-invalid.ll
…
target-abi-valid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
thread-pointer.ll [RISCV] Support llvm.thread.pointer 2020-03-27 17:30:12 -07:00
tls-models.ll Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" 2020-07-14 11:15:01 +01:00
umulo-128-legalisation-lowering.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
urem-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
urem-vector-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
vararg.ll [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move 2020-08-27 10:32:22 +01:00
verify-instr.mir Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
wide-mem.ll [RISCV] Fold ADDIs into load/stores with nonzero offsets 2020-07-06 17:32:57 +01:00
zext-with-load-is-free.ll [RISCV] Implement Hooks to avoid chaining SELECT 2020-07-01 11:56:31 +01:00