llvm-project/llvm/test/CodeGen
Martin Storsjö 6f792041a5 Reapply "[CodeGen] [WinException] Only produce handler data at the end of the function if needed"
This reapplies 36c64af9d7 in updated
form.

Emit the xdata for each function at .seh_endproc. This keeps the
exact same output header order for most code generated by the LLVM
CodeGen layer. (Sections still change order for code built from
assembly where functions lack an explicit .seh_handlerdata
directive, and functions with chained unwind info.)

The practical effect should be that assembly output lacks
superfluous ".seh_handlerdata; .text" pairs at the end of functions
that don't handle exceptions, which allows such functions to use
the AArch64 packed unwind format again.

Differential Revision: https://reviews.llvm.org/D87448
2020-11-23 23:17:03 +02:00
..
AArch64 Reapply "[CodeGen] [WinException] Only produce handler data at the end of the function if needed" 2020-11-23 23:17:03 +02:00
AMDGPU AMDGPU: Fix counting kernel arguments towards register usage 2020-11-20 21:23:33 -05:00
ARC
ARM [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets. 2020-11-23 10:09:20 -08:00
AVR [AVR] Optimize the 16-bit NEGW pseudo instruction 2020-11-17 17:51:58 +08:00
BPF OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
Generic OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
Hexagon OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
Inputs
Lanai
MIR OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
MSP430 OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
Mips OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
NVPTX OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
PowerPC [AIX] Support init priority 2020-11-23 14:50:05 -05:00
RISCV [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets. 2020-11-23 10:09:20 -08:00
SPARC OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
SystemZ OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
Thumb OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
Thumb2 [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets. 2020-11-23 10:09:20 -08:00
VE [VE] VE Vector Predicated SDNode, vector add isel and tests 2020-11-23 17:17:07 +01:00
WebAssembly OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
WinCFGuard [CFGuard] Add address-taken IAT tables and delay-load support 2020-11-17 18:24:45 -08:00
WinEH
X86 Reapply "[CodeGen] [WinException] Only produce handler data at the end of the function if needed" 2020-11-23 23:17:03 +02:00
XCore OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00