Daniel Sanders 1f6f0f4b54 [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 ... Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771		2014-06-12 11:55:58 +00:00
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nullvoid.ll	…
simplestore.ll	…
simplestorefp1.ll	[mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64	2014-06-12 11:55:58 +00:00
simplestorei.ll	Finish materialize for ints	2014-05-15 21:54:15 +00:00