llvm-project/llvm/test/CodeGen
Craig Topper 41759c3d92 [RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC.
This allows me to introduce similar combines for branches as
we have recently added for SELECT_CC. Some of them are less
useful for standalone setccs and only help branch instructions.
By having a BR_CC node its easier to only affect branches.

I'm using CondCodeSDNode to make isel patterns easier to
write so we can refer to the codes by name. SELECT_CC uses a
constant instead.

I've translated the condition code just like SELECT_CC so
we need less patterns for the swapped conditions. This
includes special cases for X < 1 and X > -1 that get translated
to blez and bgez by using a 0 constant.

computeKnownBitsForTargetNode support for SELECT_CC is added
to allow MaskedValueIsZero to work for cases where the true
and false values of the SELECT_CC are setccs and the
result of the SELECT_CC is used by a BR_CC. This was needed
to avoid regressions in some of the overflow tests.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D98159
2021-03-15 11:54:01 -07:00
..
AArch64 [AArch64] Implement __rndr, __rndrrs intrinsics 2021-03-15 17:51:48 +00:00
AMDGPU [amdgpu] Implement lower function LDS pass 2021-03-15 15:24:01 +00:00
ARC
ARM Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
AVR [AVR] Fix lifeness issues in the AVR backend 2021-03-04 14:04:39 +01:00
BPF [BPF] Add support for floats and doubles 2021-03-05 15:10:11 +01:00
Generic [PowerPC] Removing _massv place holder 2021-03-08 21:43:24 +00:00
Hexagon
Inputs
Lanai
M68k [M68k][test](6/8) Add all of the tests 2021-03-08 12:30:57 -08:00
MIR [mir] Change 'undef' for MMO base addresses to 'unknown-address' 2021-03-10 16:46:44 -08:00
MSP430
Mips Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
NVPTX [NVPTX][NewPM] Re-enable NVVMReflectPass 2021-02-08 13:58:17 -08:00
PowerPC [NFC][PowerPC] Add additional load/store test cases 2021-03-15 08:54:38 -05:00
RISCV [RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC. 2021-03-15 11:54:01 -07:00
SPARC [LegalizeTypes] Improve ExpandIntRes_XMULO codegen. 2021-03-01 09:54:32 -08:00
SystemZ [SystemZ] Reimplement the i8/i16 compare-and-swap logic. 2021-03-03 14:04:32 -06:00
Thumb Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
Thumb2 Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
VE [test] Fix CodeGen/VE/Scalar tests 2021-03-02 15:30:44 -08:00
WebAssembly [WebAssembly] Fix ExceptionInfo grouping again 2021-03-04 15:05:13 -08:00
WinCFGuard
WinEH
X86 [X86][SSE] isHorizontalBinOp - ensure we clear any unused source operands to improve HADD/SUB matching 2021-03-15 16:24:29 +00:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00