forked from OSchip/llvm-project
775 lines
19 KiB
LLVM
775 lines
19 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=CHECK --check-prefix=BMI1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefix=CHECK --check-prefix=BMI2
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declare i8 @llvm.cttz.i8(i8, i1)
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declare i16 @llvm.cttz.i16(i16, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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declare i64 @llvm.cttz.i64(i64, i1)
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define i8 @t1(i8 %x) {
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; CHECK-LABEL: t1:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: orl $256, %eax # imm = 0x100
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; CHECK-NEXT: tzcntl %eax, %eax
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; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; CHECK-NEXT: retq
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%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
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ret i8 %tmp
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}
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define i16 @t2(i16 %x) {
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; CHECK-LABEL: t2:
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; CHECK: # BB#0:
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; CHECK-NEXT: tzcntw %di, %ax
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; CHECK-NEXT: retq
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%tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 false )
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ret i16 %tmp
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}
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define i32 @t3(i32 %x) {
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; CHECK-LABEL: t3:
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; CHECK: # BB#0:
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; CHECK-NEXT: tzcntl %edi, %eax
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; CHECK-NEXT: retq
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 false )
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ret i32 %tmp
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}
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define i32 @tzcnt32_load(i32* %x) {
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; CHECK-LABEL: tzcnt32_load:
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; CHECK: # BB#0:
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; CHECK-NEXT: tzcntl (%rdi), %eax
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; CHECK-NEXT: retq
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%x1 = load i32, i32* %x
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%tmp = tail call i32 @llvm.cttz.i32(i32 %x1, i1 false )
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ret i32 %tmp
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}
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define i64 @t4(i64 %x) {
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; CHECK-LABEL: t4:
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; CHECK: # BB#0:
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; CHECK-NEXT: tzcntq %rdi, %rax
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; CHECK-NEXT: retq
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%tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 false )
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ret i64 %tmp
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}
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define i8 @t5(i8 %x) {
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; CHECK-LABEL: t5:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: tzcntl %eax, %eax
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; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; CHECK-NEXT: retq
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%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
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ret i8 %tmp
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}
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define i16 @t6(i16 %x) {
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; CHECK-LABEL: t6:
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; CHECK: # BB#0:
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; CHECK-NEXT: tzcntw %di, %ax
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; CHECK-NEXT: retq
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%tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 true )
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ret i16 %tmp
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}
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define i32 @t7(i32 %x) {
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; CHECK-LABEL: t7:
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; CHECK: # BB#0:
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; CHECK-NEXT: tzcntl %edi, %eax
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; CHECK-NEXT: retq
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
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ret i32 %tmp
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}
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define i64 @t8(i64 %x) {
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; CHECK-LABEL: t8:
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; CHECK: # BB#0:
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; CHECK-NEXT: tzcntq %rdi, %rax
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; CHECK-NEXT: retq
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%tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 true )
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ret i64 %tmp
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}
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define i32 @andn32(i32 %x, i32 %y) {
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; CHECK-LABEL: andn32:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnl %esi, %edi, %eax
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; CHECK-NEXT: retq
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%tmp1 = xor i32 %x, -1
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%tmp2 = and i32 %y, %tmp1
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ret i32 %tmp2
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}
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define i32 @andn32_load(i32 %x, i32* %y) {
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; CHECK-LABEL: andn32_load:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnl (%rsi), %edi, %eax
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; CHECK-NEXT: retq
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%y1 = load i32, i32* %y
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%tmp1 = xor i32 %x, -1
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%tmp2 = and i32 %y1, %tmp1
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ret i32 %tmp2
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}
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define i64 @andn64(i64 %x, i64 %y) {
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; CHECK-LABEL: andn64:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnq %rsi, %rdi, %rax
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; CHECK-NEXT: retq
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%tmp1 = xor i64 %x, -1
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%tmp2 = and i64 %tmp1, %y
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ret i64 %tmp2
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}
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; Don't choose a 'test' if an 'andn' can be used.
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define i1 @andn_cmp(i32 %x, i32 %y) {
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; CHECK-LABEL: andn_cmp:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnl %esi, %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%notx = xor i32 %x, -1
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%and = and i32 %notx, %y
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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; Recognize a disguised andn in the following 4 tests.
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define i1 @and_cmp1(i32 %x, i32 %y) {
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; CHECK-LABEL: and_cmp1:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnl %esi, %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, %y
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%cmp = icmp eq i32 %and, %y
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ret i1 %cmp
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}
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define i1 @and_cmp2(i32 %x, i32 %y) {
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; CHECK-LABEL: and_cmp2:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnl %esi, %edi, %eax
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: retq
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%and = and i32 %y, %x
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%cmp = icmp ne i32 %and, %y
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ret i1 %cmp
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}
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define i1 @and_cmp3(i32 %x, i32 %y) {
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; CHECK-LABEL: and_cmp3:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnl %esi, %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, %y
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%cmp = icmp eq i32 %y, %and
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ret i1 %cmp
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}
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define i1 @and_cmp4(i32 %x, i32 %y) {
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; CHECK-LABEL: and_cmp4:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnl %esi, %edi, %eax
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: retq
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%and = and i32 %y, %x
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%cmp = icmp ne i32 %y, %and
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ret i1 %cmp
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}
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; A mask and compare against constant is ok for an 'andn' too
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; even though the BMI instruction doesn't have an immediate form.
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define i1 @and_cmp_const(i32 %x) {
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; CHECK-LABEL: and_cmp_const:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $43, %eax
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; CHECK-NEXT: andnl %eax, %edi, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 43
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%cmp = icmp eq i32 %and, 43
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ret i1 %cmp
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}
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; But don't use 'andn' if the mask is a power-of-two.
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define i1 @and_cmp_const_power_of_two(i32 %x, i32 %y) {
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; CHECK-LABEL: and_cmp_const_power_of_two:
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; CHECK: # BB#0:
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; CHECK-NEXT: btl %esi, %edi
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; CHECK-NEXT: setae %al
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; CHECK-NEXT: retq
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%shl = shl i32 1, %y
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%and = and i32 %x, %shl
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%cmp = icmp ne i32 %and, %shl
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ret i1 %cmp
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}
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; Don't transform to 'andn' if there's another use of the 'and'.
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define i32 @and_cmp_not_one_use(i32 %x) {
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; CHECK-LABEL: and_cmp_not_one_use:
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; CHECK: # BB#0:
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; CHECK-NEXT: andl $37, %edi
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: cmpl $37, %edi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: addl %edi, %eax
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; CHECK-NEXT: retq
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%and = and i32 %x, 37
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%cmp = icmp eq i32 %and, 37
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%ext = zext i1 %cmp to i32
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%add = add i32 %and, %ext
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ret i32 %add
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}
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; Verify that we're not transforming invalid comparison predicates.
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define i1 @not_an_andn1(i32 %x, i32 %y) {
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; CHECK-LABEL: not_an_andn1:
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; CHECK: # BB#0:
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; CHECK-NEXT: andl %esi, %edi
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; CHECK-NEXT: cmpl %edi, %esi
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; CHECK-NEXT: setg %al
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; CHECK-NEXT: retq
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%and = and i32 %x, %y
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%cmp = icmp sgt i32 %y, %and
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ret i1 %cmp
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}
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define i1 @not_an_andn2(i32 %x, i32 %y) {
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; CHECK-LABEL: not_an_andn2:
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; CHECK: # BB#0:
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; CHECK-NEXT: andl %esi, %edi
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; CHECK-NEXT: cmpl %edi, %esi
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; CHECK-NEXT: setbe %al
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; CHECK-NEXT: retq
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%and = and i32 %y, %x
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%cmp = icmp ule i32 %y, %and
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ret i1 %cmp
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}
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; Don't choose a 'test' if an 'andn' can be used.
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define i1 @andn_cmp_swap_ops(i64 %x, i64 %y) {
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; CHECK-LABEL: andn_cmp_swap_ops:
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; CHECK: # BB#0:
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; CHECK-NEXT: andnq %rsi, %rdi, %rax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%notx = xor i64 %x, -1
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%and = and i64 %y, %notx
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%cmp = icmp eq i64 %and, 0
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ret i1 %cmp
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}
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; Use a 'test' (not an 'and') because 'andn' only works for i32/i64.
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define i1 @andn_cmp_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: andn_cmp_i8:
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; CHECK: # BB#0:
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; CHECK-NEXT: notb %sil
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; CHECK-NEXT: testb %sil, %dil
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%noty = xor i8 %y, -1
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%and = and i8 %x, %noty
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%cmp = icmp eq i8 %and, 0
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ret i1 %cmp
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}
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define i32 @bextr32(i32 %x, i32 %y) {
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; CHECK-LABEL: bextr32:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextrl %esi, %edi, %eax
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; CHECK-NEXT: retq
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%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
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ret i32 %tmp
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}
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define i32 @bextr32_load(i32* %x, i32 %y) {
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; CHECK-LABEL: bextr32_load:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextrl %esi, (%rdi), %eax
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; CHECK-NEXT: retq
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%x1 = load i32, i32* %x
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%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x1, i32 %y)
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ret i32 %tmp
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}
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declare i32 @llvm.x86.bmi.bextr.32(i32, i32)
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define i32 @bextr32b(i32 %x) uwtable ssp {
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; CHECK-LABEL: bextr32b:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $3076, %eax # imm = 0xC04
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; CHECK-NEXT: bextrl %eax, %edi, %eax
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; CHECK-NEXT: retq
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%1 = lshr i32 %x, 4
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%2 = and i32 %1, 4095
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ret i32 %2
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}
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define i32 @bextr32b_load(i32* %x) uwtable ssp {
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; CHECK-LABEL: bextr32b_load:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $3076, %eax # imm = 0xC04
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; CHECK-NEXT: bextrl %eax, (%rdi), %eax
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; CHECK-NEXT: retq
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%1 = load i32, i32* %x
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%2 = lshr i32 %1, 4
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%3 = and i32 %2, 4095
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ret i32 %3
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}
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; PR34042
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define i32 @bextr32c(i32 %x, i16 zeroext %y) {
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; CHECK-LABEL: bextr32c:
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; CHECK: # BB#0:
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; CHECK-NEXT: movswl %si, %eax
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; CHECK-NEXT: bextrl %eax, %edi, %eax
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; CHECK-NEXT: retq
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%tmp0 = sext i16 %y to i32
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%tmp1 = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %tmp0)
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ret i32 %tmp1
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}
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define i64 @bextr64(i64 %x, i64 %y) {
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; CHECK-LABEL: bextr64:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextrq %rsi, %rdi, %rax
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; CHECK-NEXT: retq
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%tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
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ret i64 %tmp
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}
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declare i64 @llvm.x86.bmi.bextr.64(i64, i64)
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define i64 @bextr64b(i64 %x) uwtable ssp {
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; CHECK-LABEL: bextr64b:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $3076, %eax # imm = 0xC04
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; CHECK-NEXT: bextrl %eax, %edi, %eax
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; CHECK-NEXT: retq
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%1 = lshr i64 %x, 4
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%2 = and i64 %1, 4095
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ret i64 %2
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}
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define i64 @bextr64b_load(i64* %x) {
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; CHECK-LABEL: bextr64b_load:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $3076, %eax # imm = 0xC04
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; CHECK-NEXT: bextrl %eax, (%rdi), %eax
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; CHECK-NEXT: retq
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%1 = load i64, i64* %x, align 8
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%2 = lshr i64 %1, 4
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%3 = and i64 %2, 4095
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ret i64 %3
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}
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; PR34042
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define i64 @bextr64c(i64 %x, i32 %y) {
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; CHECK-LABEL: bextr64c:
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; CHECK: # BB#0:
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; CHECK-NEXT: movslq %esi, %rax
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; CHECK-NEXT: bextrq %rax, %rdi, %rax
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; CHECK-NEXT: retq
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%tmp0 = sext i32 %y to i64
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%tmp1 = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %tmp0)
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ret i64 %tmp1
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}
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define i32 @non_bextr32(i32 %x) {
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; CHECK-LABEL: non_bextr32:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: shrl $2, %edi
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; CHECK-NEXT: andl $111, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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entry:
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%shr = lshr i32 %x, 2
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%and = and i32 %shr, 111
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ret i32 %and
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}
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define i64 @non_bextr64(i64 %x) {
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; CHECK-LABEL: non_bextr64:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: shrq $2, %rdi
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; CHECK-NEXT: movabsq $8589934590, %rax # imm = 0x1FFFFFFFE
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; CHECK-NEXT: andq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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%shr = lshr i64 %x, 2
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%and = and i64 %shr, 8589934590
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ret i64 %and
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}
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define i32 @bzhi32b(i32 %x, i8 zeroext %index) {
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; BMI1-LABEL: bzhi32b:
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; BMI1: # BB#0: # %entry
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; BMI1-NEXT: movl $1, %eax
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; BMI1-NEXT: movl %esi, %ecx
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; BMI1-NEXT: shll %cl, %eax
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; BMI1-NEXT: decl %eax
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; BMI1-NEXT: andl %edi, %eax
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; BMI1-NEXT: retq
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;
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; BMI2-LABEL: bzhi32b:
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; BMI2: # BB#0: # %entry
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; BMI2-NEXT: bzhil %esi, %edi, %eax
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; BMI2-NEXT: retq
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entry:
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%conv = zext i8 %index to i32
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%shl = shl i32 1, %conv
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%sub = add nsw i32 %shl, -1
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%and = and i32 %sub, %x
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ret i32 %and
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}
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define i32 @bzhi32b_load(i32* %w, i8 zeroext %index) {
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; BMI1-LABEL: bzhi32b_load:
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; BMI1: # BB#0: # %entry
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; BMI1-NEXT: movl $1, %eax
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; BMI1-NEXT: movl %esi, %ecx
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; BMI1-NEXT: shll %cl, %eax
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; BMI1-NEXT: decl %eax
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; BMI1-NEXT: andl (%rdi), %eax
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; BMI1-NEXT: retq
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;
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; BMI2-LABEL: bzhi32b_load:
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; BMI2: # BB#0: # %entry
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; BMI2-NEXT: bzhil %esi, (%rdi), %eax
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; BMI2-NEXT: retq
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entry:
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|
%x = load i32, i32* %w
|
|
%conv = zext i8 %index to i32
|
|
%shl = shl i32 1, %conv
|
|
%sub = add nsw i32 %shl, -1
|
|
%and = and i32 %sub, %x
|
|
ret i32 %and
|
|
}
|
|
|
|
define i32 @bzhi32c(i32 %x, i8 zeroext %index) {
|
|
; BMI1-LABEL: bzhi32c:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $1, %eax
|
|
; BMI1-NEXT: movl %esi, %ecx
|
|
; BMI1-NEXT: shll %cl, %eax
|
|
; BMI1-NEXT: decl %eax
|
|
; BMI1-NEXT: andl %edi, %eax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi32c:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: bzhil %esi, %edi, %eax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%conv = zext i8 %index to i32
|
|
%shl = shl i32 1, %conv
|
|
%sub = add nsw i32 %shl, -1
|
|
%and = and i32 %x, %sub
|
|
ret i32 %and
|
|
}
|
|
|
|
define i32 @bzhi32d(i32 %a, i32 %b) {
|
|
; BMI1-LABEL: bzhi32d:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $32, %ecx
|
|
; BMI1-NEXT: subl %esi, %ecx
|
|
; BMI1-NEXT: movl $-1, %eax
|
|
; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
|
|
; BMI1-NEXT: shrl %cl, %eax
|
|
; BMI1-NEXT: andl %edi, %eax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi32d:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: bzhil %esi, %edi, %eax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%sub = sub i32 32, %b
|
|
%shr = lshr i32 -1, %sub
|
|
%and = and i32 %shr, %a
|
|
ret i32 %and
|
|
}
|
|
|
|
define i32 @bzhi32e(i32 %a, i32 %b) {
|
|
; BMI1-LABEL: bzhi32e:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $32, %ecx
|
|
; BMI1-NEXT: subl %esi, %ecx
|
|
; BMI1-NEXT: shll %cl, %edi
|
|
; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
|
|
; BMI1-NEXT: shrl %cl, %edi
|
|
; BMI1-NEXT: movl %edi, %eax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi32e:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: bzhil %esi, %edi, %eax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%sub = sub i32 32, %b
|
|
%shl = shl i32 %a, %sub
|
|
%shr = lshr i32 %shl, %sub
|
|
ret i32 %shr
|
|
}
|
|
|
|
define i64 @bzhi64b(i64 %x, i8 zeroext %index) {
|
|
; BMI1-LABEL: bzhi64b:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $1, %eax
|
|
; BMI1-NEXT: movl %esi, %ecx
|
|
; BMI1-NEXT: shlq %cl, %rax
|
|
; BMI1-NEXT: decq %rax
|
|
; BMI1-NEXT: andq %rdi, %rax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi64b:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
|
|
; BMI2-NEXT: bzhiq %rsi, %rdi, %rax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%conv = zext i8 %index to i64
|
|
%shl = shl i64 1, %conv
|
|
%sub = add nsw i64 %shl, -1
|
|
%and = and i64 %x, %sub
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @bzhi64c(i64 %a, i64 %b) {
|
|
; BMI1-LABEL: bzhi64c:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $64, %ecx
|
|
; BMI1-NEXT: subl %esi, %ecx
|
|
; BMI1-NEXT: movq $-1, %rax
|
|
; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
|
|
; BMI1-NEXT: shrq %cl, %rax
|
|
; BMI1-NEXT: andq %rdi, %rax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi64c:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: bzhiq %rsi, %rdi, %rax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%sub = sub i64 64, %b
|
|
%shr = lshr i64 -1, %sub
|
|
%and = and i64 %shr, %a
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @bzhi64d(i64 %a, i32 %b) {
|
|
; BMI1-LABEL: bzhi64d:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $64, %ecx
|
|
; BMI1-NEXT: subl %esi, %ecx
|
|
; BMI1-NEXT: movq $-1, %rax
|
|
; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
|
|
; BMI1-NEXT: shrq %cl, %rax
|
|
; BMI1-NEXT: andq %rdi, %rax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi64d:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
|
|
; BMI2-NEXT: bzhiq %rsi, %rdi, %rax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%sub = sub i32 64, %b
|
|
%sh_prom = zext i32 %sub to i64
|
|
%shr = lshr i64 -1, %sh_prom
|
|
%and = and i64 %shr, %a
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @bzhi64e(i64 %a, i64 %b) {
|
|
; BMI1-LABEL: bzhi64e:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $64, %ecx
|
|
; BMI1-NEXT: subl %esi, %ecx
|
|
; BMI1-NEXT: shlq %cl, %rdi
|
|
; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
|
|
; BMI1-NEXT: shrq %cl, %rdi
|
|
; BMI1-NEXT: movq %rdi, %rax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi64e:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: bzhiq %rsi, %rdi, %rax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%sub = sub i64 64, %b
|
|
%shl = shl i64 %a, %sub
|
|
%shr = lshr i64 %shl, %sub
|
|
ret i64 %shr
|
|
}
|
|
|
|
define i64 @bzhi64f(i64 %a, i32 %b) {
|
|
; BMI1-LABEL: bzhi64f:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $64, %ecx
|
|
; BMI1-NEXT: subl %esi, %ecx
|
|
; BMI1-NEXT: shlq %cl, %rdi
|
|
; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
|
|
; BMI1-NEXT: shrq %cl, %rdi
|
|
; BMI1-NEXT: movq %rdi, %rax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi64f:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
|
|
; BMI2-NEXT: bzhiq %rsi, %rdi, %rax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%sub = sub i32 64, %b
|
|
%sh_prom = zext i32 %sub to i64
|
|
%shl = shl i64 %a, %sh_prom
|
|
%shr = lshr i64 %shl, %sh_prom
|
|
ret i64 %shr
|
|
}
|
|
|
|
define i64 @bzhi64_constant_mask(i64 %x) {
|
|
; BMI1-LABEL: bzhi64_constant_mask:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $15872, %eax # imm = 0x3E00
|
|
; BMI1-NEXT: bextrq %rax, %rdi, %rax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi64_constant_mask:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: movb $62, %al
|
|
; BMI2-NEXT: bzhiq %rax, %rdi, %rax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%and = and i64 %x, 4611686018427387903
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @bzhi64_constant_mask_load(i64* %x) {
|
|
; BMI1-LABEL: bzhi64_constant_mask_load:
|
|
; BMI1: # BB#0: # %entry
|
|
; BMI1-NEXT: movl $15872, %eax # imm = 0x3E00
|
|
; BMI1-NEXT: bextrq %rax, (%rdi), %rax
|
|
; BMI1-NEXT: retq
|
|
;
|
|
; BMI2-LABEL: bzhi64_constant_mask_load:
|
|
; BMI2: # BB#0: # %entry
|
|
; BMI2-NEXT: movb $62, %al
|
|
; BMI2-NEXT: bzhiq %rax, (%rdi), %rax
|
|
; BMI2-NEXT: retq
|
|
entry:
|
|
%x1 = load i64, i64* %x
|
|
%and = and i64 %x1, 4611686018427387903
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @bzhi64_small_constant_mask(i64 %x) {
|
|
; CHECK-LABEL: bzhi64_small_constant_mask:
|
|
; CHECK: # BB#0: # %entry
|
|
; CHECK-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF
|
|
; CHECK-NEXT: movq %rdi, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%and = and i64 %x, 2147483647
|
|
ret i64 %and
|
|
}
|
|
|
|
define i32 @blsi32(i32 %x) {
|
|
; CHECK-LABEL: blsi32:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsil %edi, %eax
|
|
; CHECK-NEXT: retq
|
|
%tmp = sub i32 0, %x
|
|
%tmp2 = and i32 %x, %tmp
|
|
ret i32 %tmp2
|
|
}
|
|
|
|
define i32 @blsi32_load(i32* %x) {
|
|
; CHECK-LABEL: blsi32_load:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsil (%rdi), %eax
|
|
; CHECK-NEXT: retq
|
|
%x1 = load i32, i32* %x
|
|
%tmp = sub i32 0, %x1
|
|
%tmp2 = and i32 %x1, %tmp
|
|
ret i32 %tmp2
|
|
}
|
|
|
|
define i64 @blsi64(i64 %x) {
|
|
; CHECK-LABEL: blsi64:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsiq %rdi, %rax
|
|
; CHECK-NEXT: retq
|
|
%tmp = sub i64 0, %x
|
|
%tmp2 = and i64 %tmp, %x
|
|
ret i64 %tmp2
|
|
}
|
|
|
|
define i32 @blsmsk32(i32 %x) {
|
|
; CHECK-LABEL: blsmsk32:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsmskl %edi, %eax
|
|
; CHECK-NEXT: retq
|
|
%tmp = sub i32 %x, 1
|
|
%tmp2 = xor i32 %x, %tmp
|
|
ret i32 %tmp2
|
|
}
|
|
|
|
define i32 @blsmsk32_load(i32* %x) {
|
|
; CHECK-LABEL: blsmsk32_load:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsmskl (%rdi), %eax
|
|
; CHECK-NEXT: retq
|
|
%x1 = load i32, i32* %x
|
|
%tmp = sub i32 %x1, 1
|
|
%tmp2 = xor i32 %x1, %tmp
|
|
ret i32 %tmp2
|
|
}
|
|
|
|
define i64 @blsmsk64(i64 %x) {
|
|
; CHECK-LABEL: blsmsk64:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsmskq %rdi, %rax
|
|
; CHECK-NEXT: retq
|
|
%tmp = sub i64 %x, 1
|
|
%tmp2 = xor i64 %tmp, %x
|
|
ret i64 %tmp2
|
|
}
|
|
|
|
define i32 @blsr32(i32 %x) {
|
|
; CHECK-LABEL: blsr32:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsrl %edi, %eax
|
|
; CHECK-NEXT: retq
|
|
%tmp = sub i32 %x, 1
|
|
%tmp2 = and i32 %x, %tmp
|
|
ret i32 %tmp2
|
|
}
|
|
|
|
define i32 @blsr32_load(i32* %x) {
|
|
; CHECK-LABEL: blsr32_load:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsrl (%rdi), %eax
|
|
; CHECK-NEXT: retq
|
|
%x1 = load i32, i32* %x
|
|
%tmp = sub i32 %x1, 1
|
|
%tmp2 = and i32 %x1, %tmp
|
|
ret i32 %tmp2
|
|
}
|
|
|
|
define i64 @blsr64(i64 %x) {
|
|
; CHECK-LABEL: blsr64:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: blsrq %rdi, %rax
|
|
; CHECK-NEXT: retq
|
|
%tmp = sub i64 %x, 1
|
|
%tmp2 = and i64 %tmp, %x
|
|
ret i64 %tmp2
|
|
}
|
|
|