forked from OSchip/llvm-project
113 lines
3.0 KiB
YAML
113 lines
3.0 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
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%ret = mul i16 %arg1, %arg2
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ret i16 %ret
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}
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define i32 @test_mul_i32(i32 %arg1, i32 %arg2) {
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%ret = mul i32 %arg1, %arg2
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ret i32 %ret
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}
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define i64 @test_mul_i64(i64 %arg1, i64 %arg2) {
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%ret = mul i64 %arg1, %arg2
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ret i64 %ret
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}
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...
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---
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name: test_mul_i16
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# ALL-LABEL: name: test_mul_i16
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
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# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: body: |
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# ALL: %0 = COPY %di
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# ALL-NEXT: %1 = COPY %si
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# ALL-NEXT: %2 = IMUL16rr %0, %1, implicit-def %eflags
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# ALL-NEXT: %ax = COPY %2
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# ALL-NEXT: RET 0, implicit %ax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s16) = COPY %edi
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%1(s16) = COPY %esi
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%2(s16) = G_MUL %0, %1
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%ax = COPY %2(s16)
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RET 0, implicit %ax
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...
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---
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name: test_mul_i32
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# ALL-LABEL: name: test_mul_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: body: |
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# ALL: %0 = COPY %edi
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# ALL-NEXT: %1 = COPY %esi
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# ALL-NEXT: %2 = IMUL32rr %0, %1, implicit-def %eflags
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# ALL-NEXT: %eax = COPY %2
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s32) = COPY %edi
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%1(s32) = COPY %esi
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%2(s32) = G_MUL %0, %1
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%eax = COPY %2(s32)
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RET 0, implicit %eax
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...
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---
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name: test_mul_i64
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# ALL-LABEL: name: test_mul_i64
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
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# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: body: |
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# ALL: %0 = COPY %rdi
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# ALL-NEXT: %1 = COPY %rsi
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# ALL-NEXT: %2 = IMUL64rr %0, %1, implicit-def %eflags
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# ALL-NEXT: %rax = COPY %2
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# ALL-NEXT: RET 0, implicit %rax
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body: |
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bb.1 (%ir-block.0):
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liveins: %rdi, %rsi
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%0(s64) = COPY %rdi
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%1(s64) = COPY %rsi
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%2(s64) = G_MUL %0, %1
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%rax = COPY %2(s64)
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RET 0, implicit %rax
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...
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