forked from OSchip/llvm-project
108 lines
2.9 KiB
LLVM
108 lines
2.9 KiB
LLVM
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
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; Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
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; CHECK-CALL-NOT: call
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; Combine words into doubleword
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declare i64 @llvm.hexagon.A4.combineri(i32, i32)
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define i64 @A4_combineri(i32 %a) {
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%z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0)
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ret i64 %z
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}
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; CHECK: = combine({{.*}},#0)
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declare i64 @llvm.hexagon.A4.combineir(i32, i32)
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define i64 @A4_combineir(i32 %a) {
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%z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a)
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ret i64 %z
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}
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; CHECK: = combine(#0,{{.*}})
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declare i64 @llvm.hexagon.A2.combineii(i32, i32)
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define i64 @A2_combineii() {
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%z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0)
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ret i64 %z
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}
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; CHECK: = combine(#0,#0)
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declare i32 @llvm.hexagon.A2.combine.hh(i32, i32)
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define i32 @A2_combine_hh(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.combine.hh(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = combine({{.*}},{{.*}})
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declare i32 @llvm.hexagon.A2.combine.hl(i32, i32)
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define i32 @A2_combine_hl(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.combine.hl(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = combine({{.*}},{{.*}})
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declare i32 @llvm.hexagon.A2.combine.lh(i32, i32)
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define i32 @A2_combine_lh(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.combine.lh(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = combine({{.*}},{{.*}})
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declare i32 @llvm.hexagon.A2.combine.ll(i32, i32)
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define i32 @A2_combine_ll(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.combine.ll(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = combine({{.*}},{{.*}})
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declare i64 @llvm.hexagon.A2.combinew(i32, i32)
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define i64 @A2_combinew(i32 %a, i32 %b) {
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%z = call i64 @llvm.hexagon.A2.combinew(i32 %a, i32 %b)
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ret i64 %z
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}
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; CHECK: = combine({{.*}},{{.*}})
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; Mux
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declare i32 @llvm.hexagon.C2.muxri(i32, i32, i32)
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define i32 @C2_muxri(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.C2.muxri(i32 %a, i32 0, i32 %b)
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ret i32 %z
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}
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; CHECK: = mux({{.*}},#0,{{.*}})
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declare i32 @llvm.hexagon.C2.muxir(i32, i32, i32)
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define i32 @C2_muxir(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.C2.muxir(i32 %a, i32 %b, i32 0)
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ret i32 %z
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}
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; CHECK: = mux({{.*}},{{.*}},#0)
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declare i32 @llvm.hexagon.C2.mux(i32, i32, i32)
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define i32 @C2_mux(i32 %a, i32 %b, i32 %c) {
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%z = call i32 @llvm.hexagon.C2.mux(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = mux({{.*}},{{.*}},{{.*}})
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; Shift word by 16
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declare i32 @llvm.hexagon.A2.aslh(i32)
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define i32 @A2_aslh(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.aslh(i32 %a)
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ret i32 %z
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}
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; CHECK: = aslh({{.*}})
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declare i32 @llvm.hexagon.A2.asrh(i32)
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define i32 @A2_asrh(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.asrh(i32 %a)
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ret i32 %z
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}
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; CHECK: = asrh({{.*}})
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; Pack high and low halfwords
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declare i64 @llvm.hexagon.S2.packhl(i32, i32)
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define i64 @S2_packhl(i32 %a, i32 %b) {
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%z = call i64 @llvm.hexagon.S2.packhl(i32 %a, i32 %b)
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ret i64 %z
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}
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; CHECK: = packhl({{.*}},{{.*}})
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