llvm-project/llvm/lib/CodeGen
Ahmed Bougacha bd6ce9a247 [CodeGen] Pass references, not pointers, to MMI helpers. NFC.
While there, rename them to follow the coding style.

llvm-svn: 287169
2016-11-16 22:25:03 +00:00
..
AsmPrinter [CodeView] Hook up CodeViewRecordIO to type serialization path. 2016-11-08 22:24:53 +00:00
GlobalISel [CodeGen] Pass references, not pointers, to MMI helpers. NFC. 2016-11-16 22:25:03 +00:00
MIRParser MIRParser: Add support for parsing vreg reg alloc hints 2016-11-15 00:03:14 +00:00
SelectionDAG [CodeGen] Pass references, not pointers, to MMI helpers. NFC. 2016-11-16 22:25:03 +00:00
AggressiveAntiDepBreaker.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
AllocationOrder.h Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
Analysis.cpp Fix memory issue in AttrBuilder::removeAttribute uses. 2016-10-27 14:48:09 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. 2016-06-17 18:11:48 +00:00
BasicTargetTransformInfo.cpp
BranchFolding.cpp Reapply: "Remove debug location from common tail when tail-merging" 2016-10-26 17:01:47 +00:00
BranchFolding.h Do not remove implicit defs in BranchFolder 2016-10-12 19:50:57 +00:00
BranchRelaxation.cpp BranchRelaxation: Fix computing indirect branch block size 2016-11-02 16:18:29 +00:00
BuiltinGCs.cpp
CMakeLists.txt Move AArch64BranchRelaxation to generic code 2016-10-06 15:38:53 +00:00
CalcSpillWeights.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
CallingConvLower.cpp CodeGen: Factor out code for tail call result compatibility check; NFC 2016-03-30 22:46:04 +00:00
CodeGen.cpp RegAllocGreedy: Properly initialize this pass, so that -run-pass will work 2016-11-14 21:50:13 +00:00
CodeGenPrepare.cpp Hoist check for TLI above all of the attempts to use it (including one 2016-11-04 06:54:00 +00:00
CountingFunctionInserter.cpp Add a counter-function insertion pass 2016-09-01 09:42:39 +00:00
CriticalAntiDepBreaker.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
CriticalAntiDepBreaker.h [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
DFAPacketizer.cpp [Packetizer] Add debugging code to stop packetization after N instructions 2016-08-19 21:12:52 +00:00
DeadMachineInstructionElim.cpp CodeGen: Give MachineBasicBlock::reverse_iterator a handle to the current MI 2016-09-11 18:51:28 +00:00
DetectDeadLanes.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
DwarfEHPrepare.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
EarlyIfConversion.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
EdgeBundles.cpp Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. 2016-08-25 00:45:04 +00:00
ExecutionDepsFix.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
ExpandISelPseudos.cpp CodeGen: Use MachineInstr& in ExpandISelPseudos, NFC 2016-06-30 23:09:39 +00:00
ExpandPostRAPseudos.cpp ExpandPostRAPseudos should transfer implicit uses, not only implicit defs 2016-07-15 22:31:14 +00:00
FaultMaps.cpp
FuncletLayout.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
GCMetadata.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
GCMetadataPrinter.cpp Reapply r276973 "Adjust Registry interface to not require plugins to export a registry" 2016-08-05 11:01:08 +00:00
GCRootLowering.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
GCStrategy.cpp Reapply r276973 "Adjust Registry interface to not require plugins to export a registry" 2016-08-05 11:01:08 +00:00
GlobalMerge.cpp Simplify code and address review comments (NFC) 2016-11-11 22:09:25 +00:00
IfConversion.cpp CodeGen/Passes: Pass MachineFunction as functor arg; NFC 2016-10-24 23:23:02 +00:00
ImplicitNullChecks.cpp [ImplicitNullChecks] Do not not handle call MachineInstrs 2016-11-16 21:45:22 +00:00
InlineSpiller.cpp Place the lowered phi instruction(s) before the DEBUG_VALUE entry 2016-09-16 14:07:29 +00:00
InterferenceCache.cpp
InterferenceCache.h
InterleavedAccessPass.cpp [InterleavedAccessPass] Remove global variable. 2016-10-18 18:59:58 +00:00
IntrinsicLowering.cpp Create llvm.addressofreturnaddress intrinsic 2016-10-12 22:13:19 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp llc: Add -start-before/-stop-before options 2016-09-23 21:46:02 +00:00
LatencyPriorityQueue.cpp Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
LexicalScopes.cpp Rewrite loops to use range-based for. (NFC) 2016-09-28 17:31:17 +00:00
LiveDebugValues.cpp Teach LiveDebugValues about lexical scopes. 2016-09-28 17:51:14 +00:00
LiveDebugVariables.cpp Remove dead code from LiveDebugVariables.cpp (NFC) 2016-09-28 21:34:23 +00:00
LiveDebugVariables.h [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
LiveInterval.cpp Create subranges for new intervals resulting from live interval splitting 2016-08-24 13:37:55 +00:00
LiveIntervalAnalysis.cpp Modify df_iterator to support post-order actions 2016-10-05 21:36:16 +00:00
LiveIntervalUnion.cpp Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
LivePhysRegs.cpp Handle non-~0 lane masks on live-in registers in LivePhysRegs 2016-10-28 20:06:37 +00:00
LiveRangeCalc.cpp LiveRangeCalc: Fix reporting of invalid vreg usage in liveness calculation 2016-09-19 16:49:45 +00:00
LiveRangeCalc.h Do not consider subreg defs as reads when computing subrange liveness 2016-09-02 19:48:55 +00:00
LiveRangeEdit.cpp MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC 2016-10-28 18:05:09 +00:00
LiveRangeUtils.h CodeGen: Refactor renameDisconnectedComponents() as a pass 2016-05-31 22:38:06 +00:00
LiveRegMatrix.cpp Move helpers into anonymous namespaces. NFC. 2016-08-06 11:13:10 +00:00
LiveStackAnalysis.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
LiveVariables.cpp Modify df_iterator to support post-order actions 2016-10-05 21:36:16 +00:00
LocalStackSlotAllocation.cpp Fix nondeterministic output in local stack slot alloc pass 2016-10-26 14:53:50 +00:00
LowLevelType.cpp GlobalISel: produce correct code for signext/zeroext ABI flags. 2016-09-21 12:57:45 +00:00
LowerEmuTLS.cpp Re-commit optimization bisect support (r267022) without new pass manager support. 2016-04-22 22:06:11 +00:00
MIRPrinter.cpp [MIRParser] Parse lane masks for register live-ins 2016-10-12 21:06:45 +00:00
MIRPrinter.h
MIRPrintingPass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
MachineBasicBlock.cpp Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC) 2016-10-01 06:46:33 +00:00
MachineBlockFrequencyInfo.cpp Turn cl::values() (for enum) from a vararg function to using C++ variadic template 2016-10-08 19:41:06 +00:00
MachineBlockPlacement.cpp Make block placement deterministic 2016-11-16 20:50:06 +00:00
MachineBranchProbabilityInfo.cpp Use the range variant of find/find_if instead of unpacking begin/end 2016-08-12 03:55:06 +00:00
MachineCSE.cpp MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC 2016-10-28 18:05:09 +00:00
MachineCombiner.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
MachineCopyPropagation.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp [MDT] Always verify machine dominfo if expensive checking is enabled. 2016-06-24 17:15:04 +00:00
MachineFunction.cpp [MachineMemOperand] Move synchronization scope and atomic orderings from SDNode to MachineMemOperand, and remove redundant getAtomic* member functions from SelectionDAG. 2016-10-15 22:01:18 +00:00
MachineFunctionPass.cpp [MFProperties][NFC] Rename clear into reset to match BitVector naming. 2016-08-26 22:09:08 +00:00
MachineFunctionPrinterPass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
MachineInstr.cpp [MachineMemOperand] Move synchronization scope and atomic orderings from SDNode to MachineMemOperand, and remove redundant getAtomic* member functions from SelectionDAG. 2016-10-15 22:01:18 +00:00
MachineInstrBundle.cpp CodeGen/Passes: Pass MachineFunction as functor arg; NFC 2016-10-24 23:23:02 +00:00
MachineLICM.cpp MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC 2016-10-28 18:05:09 +00:00
MachineLoopInfo.cpp MachineLoop: add methods findLoopControlBlock and findLoopPreheader 2016-08-15 08:22:42 +00:00
MachineModuleInfo.cpp [CodeGen] Pass references, not pointers, to MMI helpers. NFC. 2016-11-16 22:25:03 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePipeliner.cpp Remove redundant condition (PR28800) NFCI. 2016-11-14 10:40:23 +00:00
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp GlobalISel: allow CodeGen to fallback on VReg type/class issues. 2016-11-08 20:39:03 +00:00
MachineSSAUpdater.cpp Retire llvm::alignOf in favor of C++11 alignof. 2016-10-20 15:02:18 +00:00
MachineScheduler.cpp Revert "(origin/master, origin/HEAD) MachineScheduler/ScheduleDAG: Add support to skipping a node." 2016-11-11 22:39:50 +00:00
MachineSink.cpp MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC 2016-10-28 18:05:09 +00:00
MachineTraceMetrics.cpp [ADT] Change PostOrderIterator to use NodeRef. NFC. 2016-08-15 21:52:54 +00:00
MachineVerifier.cpp Modify df_iterator to support post-order actions 2016-10-05 21:36:16 +00:00
OptimizePHIs.cpp CodeGen: Avoid dereferencing end() in OptimizePHIs::OptimizeBB 2016-08-17 00:43:59 +00:00
PHIElimination.cpp MachineFunction: Introduce NoPHIs property 2016-08-23 21:19:49 +00:00
PHIEliminationUtils.cpp Place the lowered phi instruction(s) before the DEBUG_VALUE entry 2016-09-16 14:07:29 +00:00
PHIEliminationUtils.h
ParallelCG.cpp Bitcode: Change module reader functions to return an llvm::Expected. 2016-11-13 07:00:17 +00:00
PatchableFunction.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
PeepholeOptimizer.cpp Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. 2016-08-25 00:45:04 +00:00
PostRAHazardRecognizer.cpp CodeGen: Use MachineInstr& in PostRAHazardRecognizer, NFC 2016-07-01 00:50:29 +00:00
PostRASchedulerList.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
PreISelIntrinsicLowering.cpp [PM] Port PreISelIntrinsicLowering to the new PM 2016-06-24 20:13:42 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Modify df_iterator to support post-order actions 2016-10-05 21:36:16 +00:00
PseudoSourceValue.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
README.txt
RegAllocBase.cpp Create subranges for new intervals resulting from live interval splitting 2016-08-24 13:37:55 +00:00
RegAllocBase.h Recommit r265547, and r265610,r265639,r265657 on top of it, plus 2016-04-13 03:08:27 +00:00
RegAllocBasic.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegAllocFast.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegAllocGreedy.cpp [RegAllocGreedy] Record missed hint for late recoloring. 2016-11-16 01:07:12 +00:00
RegAllocPBQP.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegUsageInfoCollector.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegUsageInfoPropagate.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp RegisterCoalescer: Ignore interferences for constant physregs 2016-11-10 21:22:47 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Use the range variant of find/find_if instead of unpacking begin/end 2016-08-12 03:55:06 +00:00
RegisterScavenging.cpp [RegisterScavenger] Remove aliasing registers of operands from the candidate set 2016-09-06 10:10:21 +00:00
RegisterUsageInfo.cpp Move helpers into anonymous namespaces. NFC. 2016-08-06 11:13:10 +00:00
RenameIndependentSubregs.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
ResetMachineFunctionPass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SafeStack.cpp Test commit. 2016-10-17 19:09:19 +00:00
SafeStackColoring.cpp [safestack] Fix assertion failure in stack coloring. 2016-09-16 22:04:10 +00:00
SafeStackColoring.h StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
SafeStackLayout.cpp [safestack] Layout large allocas first to reduce fragmentation. 2016-08-02 23:21:30 +00:00
SafeStackLayout.h StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
ScheduleDAG.cpp Revert "(origin/master, origin/HEAD) MachineScheduler/ScheduleDAG: Add support to skipping a node." 2016-11-11 22:39:50 +00:00
ScheduleDAGInstrs.cpp ScheduleDAGInstrs: Move VRegUses to ScheduleDAGMILive; NFCI 2016-11-11 22:37:31 +00:00
ScheduleDAGPrinter.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
ScoreboardHazardRecognizer.cpp Replace "fallthrough" comments with LLVM_FALLTHROUGH 2016-08-17 05:10:15 +00:00
ShadowStackGCLowering.cpp [tsan] Add support for C++ exceptions into TSan (call __tsan_func_exit during unwinding), LLVM part 2016-11-14 21:41:13 +00:00
ShrinkWrap.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SjLjEHPrepare.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SlotIndexes.cpp CodeGen: Use MachineInstr& in SlotIndexes.cpp, NFC 2016-07-01 15:08:52 +00:00
SpillPlacement.cpp Reapply r263460: [SpillPlacement] Fix a quadratic behavior in spill placement. 2016-05-19 22:40:37 +00:00
SpillPlacement.h Reapply r263460: [SpillPlacement] Fix a quadratic behavior in spill placement. 2016-05-19 22:40:37 +00:00
Spiller.h Recommit r265547, and r265610,r265639,r265657 on top of it, plus 2016-04-13 03:08:27 +00:00
SplitKit.cpp Place the lowered phi instruction(s) before the DEBUG_VALUE entry 2016-09-16 14:07:29 +00:00
SplitKit.h Create subranges for new intervals resulting from live interval splitting 2016-08-24 13:37:55 +00:00
StackColoring.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
StackMapLivenessAnalysis.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
StackMaps.cpp [Stackmap] Added callsite counts to emitted function information. 2016-09-14 20:22:03 +00:00
StackProtector.cpp [CodeGen] stop short-circuiting the SSP code for sspstrong. 2016-09-20 21:30:01 +00:00
StackSlotColoring.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
TailDuplication.cpp Codegen: Tail-duplicate during placement. 2016-10-11 20:36:43 +00:00
TailDuplicator.cpp Codegen: Tail-duplicate during placement. 2016-10-11 20:36:43 +00:00
TargetFrameLoweringImpl.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
TargetInstrInfo.cpp MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC 2016-10-28 18:05:09 +00:00
TargetLoweringBase.cpp Add option to specify minimum number of entries for jump tables 2016-10-25 19:53:51 +00:00
TargetLoweringObjectFileImpl.cpp Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject. 2016-10-24 19:23:39 +00:00
TargetOptionsImpl.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
TargetPassConfig.cpp TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down. 2016-10-28 18:05:05 +00:00
TargetRegisterInfo.cpp Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
TargetSchedule.cpp TargetSchedule: Do not consider subregister definitions as reads. 2016-08-24 02:32:29 +00:00
TwoAddressInstructionPass.cpp [TwoAddressInstruction] When commuting an instruction don't assume that the destination register is operand 0. Pass it from the caller. 2016-09-11 22:10:42 +00:00
UnreachableBlockElim.cpp Modify df_iterator to support post-order actions 2016-10-05 21:36:16 +00:00
VirtRegMap.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
WinEHPrepare.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
XRayInstrumentation.cpp [XRay] Support for for tail calls for ARM no-Thumb 2016-10-18 05:54:15 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.