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llvm-project/llvm/lib/Target/RISCV
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Fraser Cormack 62c4ac764b [RISCV] Optimize splats of extracted vector elements 
This patch adds an optimization to splat-like operations where the
splatted value is extracted from a identically-sized vector. On RVV we
can splat that via vrgather.vx/vrgather.vi without dropping to scalar
beforehand.

We do have a similar VECTOR_SHUFFLE-specific optimization but that only
works on fixed-length vector types and for those with a constant splat
lane. This patch extends this optimization to make it work on
scalable-vector types and on unknown extract indices.

It is performed during fixed-vector BUILD_VECTOR lowering and during a
new DAGCombine on SPLAT_VECTOR for scalable vectors.

Reviewed By: craig.topper, khchen

Differential Revision: https://reviews.llvm.org/D118456
 		2022-02-08 10:35:25 +00:00
..
AsmParser [RISCV] Add support for Zihintpause extention 2022-02-03 20:55:47 +08:00
Disassembler Move TargetRegistry.(h|cpp) from Support to MC 2021-10-08 14:51:48 -07:00
MCTargetDesc [llvm] Use = default (NFC) 2022-02-06 22:18:35 -08:00
TargetInfo Fix shlib builds for all lib/Target/*/TargetInfo libs 2021-10-08 15:21:13 -07:00
CMakeLists.txt [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.h [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.td [RISCV] Add support for Zihintpause extention 2022-02-03 20:55:47 +08:00
RISCVAsmPrinter.cpp Move TargetRegistry.(h|cpp) from Support to MC 2021-10-08 14:51:48 -07:00
RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp [RISCV] Fix the bug in the register allocator caused by reserved BP. 2022-01-21 01:23:01 +00:00
RISCVFrameLowering.h [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
RISCVGatherScatterLowering.cpp [RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values. 2022-01-04 10:13:34 -08:00
RISCVISelDAGToDAG.cpp [RISCV] Remove a ComputeNumSignBits call from an isel special case. 2022-02-04 23:26:53 -08:00
RISCVISelDAGToDAG.h [RISCV] Add the passthru operand for RVV nomask load intrinsics. 2022-01-25 17:31:36 -08:00
RISCVISelLowering.cpp [RISCV] Optimize splats of extracted vector elements 2022-02-08 10:35:25 +00:00
RISCVISelLowering.h Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)." 2022-02-05 12:51:01 -08:00
RISCVInsertVSETVLI.cpp [llvm] Use = default (NFC) 2022-02-06 22:18:35 -08:00
RISCVInstrFormats.td [RISCV] Add strictfp support for compares. 2022-01-11 20:01:41 -08:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td [RISCV] Remove Zvamo Extention 2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp [RISCV] Remove createVirtualRegister from RISCVInstrInfo::movImm. 2022-02-03 08:34:26 -08:00
RISCVInstrInfo.h [RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode. 2021-12-14 10:17:57 -08:00
RISCVInstrInfo.td [RISCV] Add support for Zihintpause extention 2022-02-03 20:55:47 +08:00
RISCVInstrInfoA.td [RISCV] Use tablegen size for getInstSizeInBytes. 2022-01-28 09:21:28 -08:00
RISCVInstrInfoC.td [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets 2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00
RISCVInstrInfoF.td [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00
RISCVInstrInfoM.td [RISCV] Use MULHU for more division by constant cases. 2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td [RISCV] Remove Zvlsseg extension. 2022-01-20 12:40:07 -08:00
RISCVInstrInfoVPseudos.td [RISCV] Remove RISCVISD::SPLAT_VECTOR_I64 in favor of RISCVISD::VMV_V_X_VL. 2022-02-03 08:30:25 -08:00
RISCVInstrInfoVSDPatterns.td [RISCV] Use splat_vector instead of SplatPat in widening FP instruction patterns. NFCI 2022-02-07 15:53:27 -08:00
RISCVInstrInfoVVLPatterns.td [RISCV] Remove RISCVISD::SPLAT_VECTOR_I64 in favor of RISCVISD::VMV_V_X_VL. 2022-02-03 08:30:25 -08:00
RISCVInstrInfoZb.td [RISCV] Lower riscv_zip/unzip intrinsic to RISCVISD::SHFL/UNSHFL. 2022-01-30 13:27:41 -08:00
RISCVInstrInfoZfh.td Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)." 2022-02-05 12:51:01 -08:00
RISCVInstrInfoZk.td [RISCV] Adjust some comments. 2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp [Target] Remove redundant member initialization (NFC) 2022-01-06 22:01:44 -08:00
RISCVLegalizerInfo.cpp [globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one 2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp [NFC] Use Register instead of unsigned 2022-01-19 20:17:04 +08:00
RISCVMachineFunctionInfo.h
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RISCVMergeBaseOffset.cpp [RISCV] Remove unused member variable. NFC 2021-10-14 12:56:47 -07:00
RISCVRedundantCopyElimination.cpp [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp Revert "[llvm] Remove redundant member initialization (NFC)" 2022-01-03 11:28:47 -08:00
RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp Reduce dependencies on llvm/BinaryFormat/Dwarf.h 2022-02-04 11:44:03 +01:00
RISCVRegisterInfo.h [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
RISCVSExtWRemoval.cpp [RISCV] Add FMV_X_W and FMV_X_H to RISCVSExtWRemoval. 2022-02-03 09:40:47 -08:00
RISCVSchedRocket.td [RISCV] add support for zbkx subextension in MC layer. 2022-01-24 20:38:46 +08:00
RISCVSchedSiFive7.td [RISCV] add support for zbkx subextension in MC layer. 2022-01-24 20:38:46 +08:00
RISCVSchedule.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVScheduleB.td [RISCV] Add instruction schedule for Zbc extension and Zbs extension 2022-01-18 07:31:50 +00:00
RISCVScheduleV.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp [RISCV] Fix support of vlen = 64. 2022-01-26 16:31:21 +08:00
RISCVSubtarget.h [RISCV] Add support for Zihintpause extention 2022-02-03 20:55:47 +08:00
RISCVSystemOperands.td [RISCV] Initially support the K-extension instructions on the LLVM MC layer 2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp [RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters 2022-01-17 15:27:54 +08:00
RISCVTargetTransformInfo.h [RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters 2022-01-17 15:27:54 +08:00