forked from OSchip/llvm-project
127 lines
5.2 KiB
C
127 lines
5.2 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s
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#include <arm_sve.h>
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// CHECK-LABEL: @test_svindex_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 [[BASE:%.*]], i8 [[STEP:%.*]])
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// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z15test_svindex_s8aa(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 [[BASE:%.*]], i8 [[STEP:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
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//
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svint8_t test_svindex_s8(int8_t base, int8_t step)
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{
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return svindex_s8(base, step);
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}
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// CHECK-LABEL: @test_svindex_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 [[BASE:%.*]], i16 [[STEP:%.*]])
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// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svindex_s16ss(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 [[BASE:%.*]], i16 [[STEP:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
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//
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svint16_t test_svindex_s16(int16_t base, int16_t step)
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{
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return svindex_s16(base, step);
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}
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// CHECK-LABEL: @test_svindex_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 [[BASE:%.*]], i32 [[STEP:%.*]])
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svindex_s32ii(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 [[BASE:%.*]], i32 [[STEP:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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svint32_t test_svindex_s32(int32_t base, int32_t step)
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{
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return svindex_s32(base, step);
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}
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// CHECK-LABEL: @test_svindex_s64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 [[BASE:%.*]], i64 [[STEP:%.*]])
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svindex_s64ll(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 [[BASE:%.*]], i64 [[STEP:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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svint64_t test_svindex_s64(int64_t base, int64_t step)
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{
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return svindex_s64(base, step);
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}
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// CHECK-LABEL: @test_svindex_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 [[BASE:%.*]], i8 [[STEP:%.*]])
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// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z15test_svindex_u8hh(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 [[BASE:%.*]], i8 [[STEP:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
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//
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svuint8_t test_svindex_u8(uint8_t base, uint8_t step)
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{
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return svindex_u8(base, step);
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}
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// CHECK-LABEL: @test_svindex_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 [[BASE:%.*]], i16 [[STEP:%.*]])
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// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svindex_u16tt(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 [[BASE:%.*]], i16 [[STEP:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
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//
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svuint16_t test_svindex_u16(uint16_t base, uint16_t step)
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{
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return svindex_u16(base, step);
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}
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// CHECK-LABEL: @test_svindex_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 [[BASE:%.*]], i32 [[STEP:%.*]])
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svindex_u32jj(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 [[BASE:%.*]], i32 [[STEP:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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svuint32_t test_svindex_u32(uint32_t base, uint32_t step)
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{
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return svindex_u32(base, step);
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}
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// CHECK-LABEL: @test_svindex_u64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 [[BASE:%.*]], i64 [[STEP:%.*]])
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svindex_u64mm(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 [[BASE:%.*]], i64 [[STEP:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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svuint64_t test_svindex_u64(uint64_t base, uint64_t step)
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{
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return svindex_u64(base, step);
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}
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