forked from OSchip/llvm-project
108 lines
4.2 KiB
LLVM
108 lines
4.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.AMDGPU.cvt.f32.ubyte0(i32) nounwind readnone
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declare float @llvm.AMDGPU.cvt.f32.ubyte1(i32) nounwind readnone
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declare float @llvm.AMDGPU.cvt.f32.ubyte2(i32) nounwind readnone
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declare float @llvm.AMDGPU.cvt.f32.ubyte3(i32) nounwind readnone
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; SI-LABEL: {{^}}test_unpack_byte0_to_float:
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; SI: v_cvt_f32_ubyte0
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define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte0(i32 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_unpack_byte1_to_float:
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; SI: v_cvt_f32_ubyte1
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define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_unpack_byte2_to_float:
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; SI: v_cvt_f32_ubyte2
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define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_unpack_byte3_to_float:
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; SI: v_cvt_f32_ubyte3
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define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte3(i32 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}byte1_shift8:
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; SI: buffer_load_dword [[VAL:v[0-9]+]]
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; SI-NOT: [[VAL]]
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; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]]
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; SI: buffer_store_dword [[CONV]]
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define void @byte1_shift8(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%shift = lshr i32 %val, 8
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}byte1_shift7:
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; SI: buffer_load_dword [[VAL:v[0-9]+]]
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; SI: v_lshrrev_b32_e32 [[SRL:v[0-9]+]], 7, [[VAL]]
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; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[SRL]]
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; SI: buffer_store_dword [[CONV]]
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define void @byte1_shift7(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%shift = lshr i32 %val, 7
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}byte1_shift16:
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; SI: buffer_load_dword [[VAL:v[0-9]+]]
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; SI-NOT: [[VAL]]
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; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]]
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; SI: buffer_store_dword [[CONV]]
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define void @byte1_shift16(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%shift = lshr i32 %val, 16
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}byte2_shift8:
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; SI: buffer_load_dword [[VAL:v[0-9]+]]
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; SI-NOT: [[VAL]]
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; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]]
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; SI: buffer_store_dword [[CONV]]
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define void @byte2_shift8(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%shift = lshr i32 %val, 8
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %shift) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; XXX - undef
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; SI-LABEL: {{^}}byte1_shift24:
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; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], 0
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; SI: buffer_store_dword [[CONV]]
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define void @byte1_shift24(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%shift = lshr i32 %val, 24
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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