forked from OSchip/llvm-project
225 lines
7.4 KiB
LLVM
225 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine -S < %s | FileCheck %s
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define i32 @cttz_abs(i32 %x) {
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; CHECK-LABEL: @cttz_abs(
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp slt i32 %x, 0
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %s, i32 %x
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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define <2 x i64> @cttz_abs_vec(<2 x i64> %x) {
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; CHECK-LABEL: @cttz_abs_vec(
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; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false)
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; CHECK-NEXT: ret <2 x i64> [[R]]
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;
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%c = icmp slt <2 x i64> %x, zeroinitializer
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%s = sub <2 x i64> zeroinitializer, %x
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%d = select <2 x i1> %c, <2 x i64> %s, <2 x i64> %x
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%r = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %d)
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ret <2 x i64> %r
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}
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define i32 @cttz_abs2(i32 %x) {
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; CHECK-LABEL: @cttz_abs2(
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; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], 0
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; CHECK-NEXT: call void @use_cond(i1 [[C]])
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp sgt i32 %x, 0
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call void @use_cond(i1 %c)
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %x, i32 %s
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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define i32 @cttz_abs3(i32 %x) {
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; CHECK-LABEL: @cttz_abs3(
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; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: call void @use_cond(i1 [[C]])
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp sgt i32 %x, -1
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call void @use_cond(i1 %c)
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %x, i32 %s
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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define i32 @cttz_abs4(i32 %x) {
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; CHECK-LABEL: @cttz_abs4(
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp slt i32 %x, 1
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %s, i32 %x
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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define i32 @cttz_nabs(i32 %x) {
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; CHECK-LABEL: @cttz_nabs(
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp slt i32 %x, 0
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %x, i32 %s
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 false)
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ret i32 %r
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}
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define <2 x i64> @cttz_nabs_vec(<2 x i64> %x) {
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; CHECK-LABEL: @cttz_nabs_vec(
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; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false)
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; CHECK-NEXT: ret <2 x i64> [[R]]
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;
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%c = icmp slt <2 x i64> %x, zeroinitializer
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%s = sub <2 x i64> zeroinitializer, %x
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%d = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %s
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%r = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %d)
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ret <2 x i64> %r
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}
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define i64 @cttz_abs_64(i64 %x) {
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; CHECK-LABEL: @cttz_abs_64(
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; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range !1
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; CHECK-NEXT: ret i64 [[R]]
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;
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%c = icmp slt i64 %x, 0
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%s = sub i64 0, %x
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%d = select i1 %c, i64 %s, i64 %x
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%r = tail call i64 @llvm.cttz.i64(i64 %d)
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ret i64 %r
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}
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define i32 @cttz_abs_multiuse(i32 %x) {
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; CHECK-LABEL: @cttz_abs_multiuse(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 0
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; CHECK-NEXT: [[S:%.*]] = sub i32 0, [[X]]
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; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[S]], i32 [[X]]
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; CHECK-NEXT: call void @use_abs(i32 [[D]])
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp slt i32 %x, 1
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %s, i32 %x
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call void @use_abs(i32 %d)
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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define i32 @cttz_nabs_multiuse(i32 %x) {
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; CHECK-LABEL: @cttz_nabs_multiuse(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 0
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; CHECK-NEXT: [[S:%.*]] = sub i32 0, [[X]]
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; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[S]]
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; CHECK-NEXT: call void @use_abs(i32 [[D]])
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp slt i32 %x, 1
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %x, i32 %s
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call void @use_abs(i32 %d)
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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; Negative tests
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define i32 @no_cttz_abs(i32 %x) {
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; CHECK-LABEL: @no_cttz_abs(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 2
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; CHECK-NEXT: [[S:%.*]] = sub i32 0, [[X]]
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; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[S]], i32 [[X]]
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp slt i32 %x, 2
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %s, i32 %x
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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define i32 @no_cttz_abs2(i32 %x) {
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; CHECK-LABEL: @no_cttz_abs2(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 0
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; CHECK-NEXT: [[S:%.*]] = sub i32 1, [[X]]
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; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[S]], i32 [[X]]
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp slt i32 %x, 0
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%s = sub i32 1, %x
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%d = select i1 %c, i32 %s, i32 %x
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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define i32 @no_cttz_abs3(i32 %x) {
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; CHECK-LABEL: @no_cttz_abs3(
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; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], -2
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; CHECK-NEXT: call void @use_cond(i1 [[C]])
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; CHECK-NEXT: [[S:%.*]] = sub i32 0, [[X]]
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; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[S]]
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; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range !0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp sgt i32 %x, -2
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call void @use_cond(i1 %c)
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%s = sub i32 0, %x
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%d = select i1 %c, i32 %x, i32 %s
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%r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
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ret i32 %r
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}
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define <2 x i64> @no_cttz_abs_vec(<2 x i64> %x) {
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; CHECK-LABEL: @no_cttz_abs_vec(
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; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[X:%.*]], <i64 2, i64 1>
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; CHECK-NEXT: [[S:%.*]] = sub <2 x i64> <i64 1, i64 0>, [[X]]
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; CHECK-NEXT: [[D:%.*]] = select <2 x i1> [[C]], <2 x i64> [[S]], <2 x i64> [[X]]
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; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false)
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; CHECK-NEXT: ret <2 x i64> [[R]]
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;
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%c = icmp slt <2 x i64> %x, <i64 2, i64 1>
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%s = sub <2 x i64> <i64 1, i64 0>, %x
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%d = select <2 x i1> %c, <2 x i64> %s, <2 x i64> %x
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%r = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %d)
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ret <2 x i64> %r
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}
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define <2 x i64> @no_cttz_nabs_vec(<2 x i64> %x) {
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; CHECK-LABEL: @no_cttz_nabs_vec(
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; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[X:%.*]], <i64 2, i64 1>
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; CHECK-NEXT: [[S:%.*]] = sub <2 x i64> <i64 1, i64 0>, [[X]]
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; CHECK-NEXT: [[D:%.*]] = select <2 x i1> [[C]], <2 x i64> [[X]], <2 x i64> [[S]]
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; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false)
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; CHECK-NEXT: ret <2 x i64> [[R]]
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;
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%c = icmp slt <2 x i64> %x, <i64 2, i64 1>
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%s = sub <2 x i64> <i64 1, i64 0>, %x
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%d = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %s
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%r = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %d)
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ret <2 x i64> %r
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}
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declare void @use_cond(i1)
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declare void @use_abs(i32)
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declare i32 @llvm.cttz.i32(i32, i1)
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declare i64 @llvm.cttz.i64(i64)
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>)
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