llvm-project/llvm/test/MC/Disassembler
Ulrich Weigand 03ab2e2b1c [SystemZ] Add all remaining instructions
This adds all remaining instructions that were still missing, mostly
privileged and semi-privileged system-level instructions.  These are
provided for use with the assembler and disassembler only.

This brings the LLVM assembler / disassembler to parity with the
GNU binutils tools.

llvm-svn: 306876
2017-06-30 20:43:40 +00:00
..
AArch64 [AArch64] armv8-A doesn't have CRC. 2017-05-03 20:33:52 +00:00
AMDGPU [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
ARM [ARM] Saturation instructions are DSP-only 2016-07-25 22:25:25 +00:00
Hexagon [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
Lanai [lanai] Add Lanai backend. 2016-03-28 13:09:54 +00:00
Mips Reland r306095: [mips] Fix reg positions in the aui/daui instructions 2017-06-23 22:37:19 +00:00
PowerPC [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions. 2017-06-12 17:58:42 +00:00
Sparc This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
SystemZ [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
X86 [X86] Adding vpopcntd and vpopcntq instructions 2017-05-25 13:45:23 +00:00
XCore