forked from OSchip/llvm-project
100 lines
3.9 KiB
C++
100 lines
3.9 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the InstructionSelect class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#define DEBUG_TYPE "instruction-select"
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using namespace llvm;
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char InstructionSelect::ID = 0;
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INITIALIZE_PASS(InstructionSelect, DEBUG_TYPE,
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"Select target instructions out of generic instructions",
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false, false);
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InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) {
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initializeInstructionSelectPass(*PassRegistry::getPassRegistry());
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}
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static void reportSelectionError(const MachineInstr &MI, const Twine &Message) {
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const MachineFunction &MF = *MI.getParent()->getParent();
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std::string ErrStorage;
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raw_string_ostream Err(ErrStorage);
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Err << Message << ":\nIn function: " << MF.getName() << '\n' << MI << '\n';
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report_fatal_error(Err.str());
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}
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bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
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const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
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assert(ISel && "Cannot work without InstructionSelector");
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// FIXME: freezeReservedRegs is now done in IRTranslator, but there are many
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// other MF/MFI fields we need to initialize.
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#ifndef NDEBUG
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// FIXME: We could introduce new blocks and will need to fix the outer loop.
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// Until then, keep track of the number of blocks to assert that we don't.
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const size_t NumBlocks = MF.size();
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#endif
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for (MachineBasicBlock *MBB : post_order(&MF)) {
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for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
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End = MBB->rend();
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MII != End;) {
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MachineInstr &MI = *MII++;
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DEBUG(dbgs() << "Selecting: " << MI << '\n');
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if (!ISel->select(MI))
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reportSelectionError(MI, "Cannot select");
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// FIXME: It would be nice to dump all inserted instructions. It's not
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// obvious how, esp. considering select() can insert after MI.
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}
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}
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assert(MF.size() == NumBlocks && "Inserting blocks is not supported yet");
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// Check that we did select everything. Do this separately to make sure we
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// didn't miss any newly inserted instructions.
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// FIXME: This (and other checks) should move into a verifier, predicated on
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// a "post-isel" MachineFunction property. That would also let us selectively
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// enable it depending on build configuration.
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if (isPreISelGenericOpcode(MI.getOpcode())) {
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reportSelectionError(
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MI, "Generic instruction survived instruction selection");
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}
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}
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}
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// Now that selection is complete, there are no more generic vregs.
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// FIXME: We're still discussing what to do with the vreg->size map:
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// it's somewhat redundant (with the def MIs type size), but having to
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// examine MIs is also awkward. Another alternative is to track the type on
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// the vreg instead, but that's not ideal either, because it's saying that
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// vregs have types, which they really don't. But then again, LLT is just
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// a size and a "shape": it's probably the same information as regbank info.
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MF.getRegInfo().clearVirtRegSizes();
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// FIXME: Should we accurately track changes?
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return true;
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}
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