Sam Elliott fafec5155e [RISCV] Allow parsing dot '.' in assembly ... Summary: Useful for jumps, such as `j .`. I am not sure who should review this. Do not hesitate to change the reviewers if needed. Reviewers: asb, jrtc27, lenary Reviewed By: lenary Subscribers: MaskRay, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63669 Patch by John LLVM (JohnLLVM) llvm-svn: 365881		2019-07-12 08:36:07 +00:00
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AsmParser	[RISCV] Allow parsing dot '.' in assembly	2019-07-12 08:36:07 +00:00
Disassembler	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
MCTargetDesc	[RISCV] Add pseudo instruction for calls with explicit register	2019-06-26 10:35:58 +00:00
TargetInfo	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
Utils	[RISCV] Add lowering of global TLS addresses	2019-06-19 08:40:59 +00:00
CMakeLists.txt	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
LLVMBuild.txt	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
RISCV.h	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCV.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVAsmPrinter.cpp	[RISCV] Support z and i operand modifiers	2019-07-08 05:00:26 +00:00
RISCVCallingConv.td	[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs	2019-03-30 17:59:30 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Add lowering of global TLS addresses	2019-06-19 08:40:59 +00:00
RISCVFrameLowering.cpp	[RISCV] Add CFI directives for RISCV prologue/epilog.	2019-06-12 03:04:22 +00:00
RISCVFrameLowering.h	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Support @llvm.readcyclecounter() Intrinsic	2019-07-05 12:35:21 +00:00
RISCVISelLowering.cpp	[RISCV] Fix ICE in isDesirableToCommuteWithShift	2019-07-09 16:24:16 +00:00
RISCVISelLowering.h	[RISCV] Specify registers used in DWARF exception handling	2019-07-08 09:16:47 +00:00
RISCVInstrFormats.td	[RISCV] Implement pseudo instructions for load/store from a symbol address.	2019-02-20 03:31:32 +00:00
RISCVInstrFormatsC.td	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVInstrInfo.cpp	[RISCV] Add pseudo instruction for calls with explicit register	2019-06-26 10:35:58 +00:00
RISCVInstrInfo.h	Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI	2019-01-25 20:22:49 +00:00
RISCVInstrInfo.td	[RISCV] Support @llvm.readcyclecounter() Intrinsic	2019-07-05 12:35:21 +00:00
RISCVInstrInfoA.td	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVInstrInfoC.td	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
RISCVInstrInfoD.td	[RISCV] Add seto pattern expansion	2019-04-01 09:54:14 +00:00
RISCVInstrInfoF.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVInstrInfoM.td	[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M	2019-01-25 05:11:34 +00:00
RISCVMCInstLower.cpp	[RISCV] Add lowering of global TLS addresses	2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Delete a ctor that is commented out. NFC	2019-07-05 08:25:14 +00:00
RISCVMergeBaseOffset.cpp	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVRegisterInfo.cpp	CodeGen: Introduce a class for registers	2019-06-24 15:50:29 +00:00
RISCVRegisterInfo.h	CodeGen: Introduce a class for registers	2019-06-24 15:50:29 +00:00
RISCVRegisterInfo.td	[RISCV] Allow fp as an alias of s0	2019-03-11 21:35:26 +00:00
RISCVSubtarget.cpp	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
RISCVSubtarget.h	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
RISCVSystemOperands.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
RISCVTargetMachine.h	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
RISCVTargetObjectFile.cpp	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetObjectFile.h	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp	[RISCV] Fix RISCVTTIImpl::getIntImmCost for immediates where getMinSignedBits() > 64	2019-07-09 10:56:18 +00:00
RISCVTargetTransformInfo.h	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00