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AArch64
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GlobalISel: support selecting fpext/fptrunc instructions on AArch64.
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2016-11-08 17:44:07 +00:00 |
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AMDGPU
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[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies
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2016-11-07 23:04:50 +00:00 |
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ARM
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[Thumb1] Move padding earlier when synthesizing TBBs off of the PC
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2016-11-07 13:38:21 +00:00 |
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AVR
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[RegAllocGreedy] Attempt to split unspillable live intervals
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2016-10-11 01:04:36 +00:00 |
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BPF
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Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
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2016-10-13 20:23:25 +00:00 |
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Generic
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Add -O0 support for @llvm.invariant.group.barrier by discarding it if it gets to ISel.
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2016-11-07 16:47:20 +00:00 |
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Hexagon
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[Hexagon] Account for <def,read-undef> when validating moves for predication
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2016-11-04 20:41:03 +00:00 |
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Inputs
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Lanai
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Add a REQUIRES: assert on a Lanai test that uses a -debug-only flag
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2016-07-29 19:35:22 +00:00 |
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MIR
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AMDGPU: Preserve vcc undef flags when inverting branch
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2016-11-07 19:09:27 +00:00 |
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MSP430
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Fix PR27500: on MSP430 the branch destination offset is measured in words, not bytes.
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2016-11-08 17:19:59 +00:00 |
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Mips
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[mips] Renable small data section test.
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2016-11-08 13:03:45 +00:00 |
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NVPTX
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[NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass.
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2016-10-31 21:51:42 +00:00 |
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PowerPC
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[PowerPC] Implement vector shift builtins - llvm portion
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2016-11-01 09:42:32 +00:00 |
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SPARC
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[Sparc][LEON] Test for FixFDIVSQRT erratum fix.
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2016-11-01 14:23:37 +00:00 |
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SystemZ
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[SystemZ] Do not use LOC(G) for volatile loads
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2016-10-25 15:39:15 +00:00 |
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Thumb
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Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"
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2016-11-03 14:08:01 +00:00 |
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Thumb2
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Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"
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2016-11-03 14:08:01 +00:00 |
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WebAssembly
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[WebAssembly] Convert stackified IMPLICIT_DEF into constant 0.
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2016-11-08 19:40:38 +00:00 |
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WinEH
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Revert EH-specific checks in BranchFolding that were causing blow ups in compile time.
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2016-07-27 17:55:33 +00:00 |
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X86
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[AVX-512] Add test cases to demonstrate PR30947. We accidentally use 32 byte aligned store instructions when the original store was only 16 byte aligned if the store is from the lower bits of a subvector extract.
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2016-11-09 05:31:53 +00:00 |
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XCore
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Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
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2016-10-13 20:23:25 +00:00 |
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