llvm-project/llvm/lib/Target/RISCV
Fangrui Song 8e8a75ad50 [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
Except AMDGPU/R600RegisterInfo (a bunch of MIR tests seem to have
problems), every target overrides it with true. PostMachineScheduler
requires livein information. Not providing it can cause assertion
failures in ScheduleDAGInstrs::addSchedBarrierDeps().
2020-01-19 14:20:37 -08:00
..
AsmParser Revert "[RISCV] Support ABI checking with per function target-features" 2020-01-16 18:01:07 -08:00
Disassembler CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
MCTargetDesc CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
Utils Revert "[RISCV] Support ABI checking with per function target-features" 2020-01-16 18:01:07 -08:00
CMakeLists.txt [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
LLVMBuild.txt [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCV.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCV.td [RISCV] Improve assembler missing feature warnings 2019-12-10 16:44:48 +00:00
RISCVAsmPrinter.cpp CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
RISCVCallLowering.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVCallLowering.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVCallingConv.td [RISCV] Rename FPRs and use Register arithmetic 2019-09-27 15:49:10 +00:00
RISCVExpandPseudoInsts.cpp [RISCV] Use addi rather than add x0 2019-11-14 18:43:38 +00:00
RISCVFrameLowering.cpp [RISCV] Allow shrink wrapping for RISC-V 2020-01-14 18:59:11 +00:00
RISCVFrameLowering.h [RISCV] Handle variable sized objects with the stack need to be realigned 2019-11-16 12:39:53 +08:00
RISCVISelDAGToDAG.cpp [SelectionDAG] Disallow indirect "i" constraint 2019-12-29 16:50:42 -08:00
RISCVISelLowering.cpp Revert "[RISCV] Support ABI checking with per function target-features" 2020-01-16 18:01:07 -08:00
RISCVISelLowering.h CodeGen: Use LLT instead of EVT in getRegisterByName 2020-01-09 17:37:52 -05:00
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp [Transforms][RISCV] Remove a "using namespace llvm" from an include file. Fix a place that became dependent on it. 2020-01-16 20:50:41 -08:00
RISCVInstrInfo.h [RISCV] Enable the machine outliner for RISC-V 2019-12-19 16:41:53 +00:00
RISCVInstrInfo.td Fix typo "psuedo" in comments 2020-01-03 14:05:58 +00:00
RISCVInstrInfoA.td [RISCV] Check register class for AMO memory operands 2020-01-13 00:50:37 +00:00
RISCVInstrInfoC.td [RISCV] Added missing ImmLeaf predicates 2019-10-04 23:42:07 +00:00
RISCVInstrInfoD.td [RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32) 2019-11-26 14:26:31 +00:00
RISCVInstrInfoF.td [RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr) 2019-10-03 15:47:28 +00:00
RISCVInstrInfoM.td
RISCVInstructionSelector.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVMCInstLower.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h [RISCV] Delete a ctor that is commented out. NFC 2019-07-05 08:25:14 +00:00
RISCVMergeBaseOffset.cpp [RISCV] Convert registers from unsigned to Register 2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVRegisterBankInfo.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVRegisterBanks.td [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp [RISCV] Handle variable sized objects with the stack need to be realigned 2019-11-16 12:39:53 +08:00
RISCVRegisterInfo.h [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
RISCVRegisterInfo.td [RISCV] Rename FPRs and use Register arithmetic 2019-09-27 15:49:10 +00:00
RISCVSubtarget.cpp [RISCV] Add support for -ffixed-xX flags 2019-10-22 21:25:01 +01:00
RISCVSubtarget.h [RISCV] Add support for -ffixed-xX flags 2019-10-22 21:25:01 +01:00
RISCVSystemOperands.td [RISCV][NFC] Replace hard-coded CSR duplication with symbolic references 2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
RISCVTargetMachine.h [RISCV] Add subtargets initialized with target feature 2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp Revert "Honor -fuse-init-array when os is not specified on x86" 2019-12-17 07:36:59 -08:00
RISCVTargetObjectFile.h [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp Rename TTI::getIntImmCost for instructions and intrinsics 2019-12-11 18:00:20 -08:00
RISCVTargetTransformInfo.h Rename TTI::getIntImmCost for instructions and intrinsics 2019-12-11 18:00:20 -08:00