forked from OSchip/llvm-project
296 lines
9.5 KiB
C++
296 lines
9.5 KiB
C++
//===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Hexagon specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
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#include "HexagonDepArch.h"
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#include "HexagonFrameLowering.h"
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#include "HexagonISelLowering.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSelectionDAGInfo.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include <memory>
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#include <string>
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#include <vector>
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#define GET_SUBTARGETINFO_HEADER
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#include "HexagonGenSubtargetInfo.inc"
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namespace llvm {
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class MachineInstr;
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class SDep;
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class SUnit;
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class TargetMachine;
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class Triple;
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class HexagonSubtarget : public HexagonGenSubtargetInfo {
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virtual void anchor();
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bool UseHVX64BOps = false;
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bool UseHVX128BOps = false;
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bool UseCompound = false;
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bool UseLongCalls = false;
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bool UseMemops = false;
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bool UsePackets = false;
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bool UseNewValueJumps = false;
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bool UseNewValueStores = false;
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bool UseSmallData = false;
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bool UseZRegOps = false;
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bool HasPreV65 = false;
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bool HasMemNoShuf = false;
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bool EnableDuplex = false;
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bool ReservedR19 = false;
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bool NoreturnStackElim = false;
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public:
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Hexagon::ArchEnum HexagonArchVersion;
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Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
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CodeGenOpt::Level OptLevel;
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/// True if the target should use Back-Skip-Back scheduling. This is the
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/// default for V60.
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bool UseBSBScheduling;
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struct UsrOverflowMutation : public ScheduleDAGMutation {
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void apply(ScheduleDAGInstrs *DAG) override;
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};
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struct HVXMemLatencyMutation : public ScheduleDAGMutation {
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void apply(ScheduleDAGInstrs *DAG) override;
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};
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struct CallMutation : public ScheduleDAGMutation {
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void apply(ScheduleDAGInstrs *DAG) override;
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private:
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bool shouldTFRICallBind(const HexagonInstrInfo &HII,
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const SUnit &Inst1, const SUnit &Inst2) const;
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};
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struct BankConflictMutation : public ScheduleDAGMutation {
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void apply(ScheduleDAGInstrs *DAG) override;
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};
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private:
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std::string CPUString;
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HexagonInstrInfo InstrInfo;
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HexagonRegisterInfo RegInfo;
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HexagonTargetLowering TLInfo;
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HexagonSelectionDAGInfo TSInfo;
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HexagonFrameLowering FrameLowering;
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InstrItineraryData InstrItins;
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public:
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HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const TargetMachine &TM);
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/// getInstrItins - Return the instruction itineraries based on subtarget
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/// selection.
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const HexagonRegisterInfo *getRegisterInfo() const override {
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return &RegInfo;
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}
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const HexagonTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const HexagonFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
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StringRef FS);
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool hasV5Ops() const {
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return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
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}
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bool hasV5OpsOnly() const {
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return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
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}
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bool hasV55Ops() const {
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return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
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}
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bool hasV55OpsOnly() const {
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return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
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}
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bool hasV60Ops() const {
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return getHexagonArchVersion() >= Hexagon::ArchEnum::V60;
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}
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bool hasV60OpsOnly() const {
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return getHexagonArchVersion() == Hexagon::ArchEnum::V60;
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}
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bool hasV62Ops() const {
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return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
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}
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bool hasV62OpsOnly() const {
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return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
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}
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bool hasV65Ops() const {
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return getHexagonArchVersion() >= Hexagon::ArchEnum::V65;
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}
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bool hasV65OpsOnly() const {
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return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
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}
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bool hasV66Ops() const {
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return getHexagonArchVersion() >= Hexagon::ArchEnum::V66;
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}
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bool hasV66OpsOnly() const {
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return getHexagonArchVersion() == Hexagon::ArchEnum::V66;
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}
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bool useCompound() const { return UseCompound; }
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bool useLongCalls() const { return UseLongCalls; }
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bool useMemops() const { return UseMemops; }
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bool usePackets() const { return UsePackets; }
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bool useNewValueJumps() const { return UseNewValueJumps; }
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bool useNewValueStores() const { return UseNewValueStores; }
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bool useSmallData() const { return UseSmallData; }
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bool useZRegOps() const { return UseZRegOps; }
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bool useHVXOps() const {
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return HexagonHVXVersion > Hexagon::ArchEnum::NoArch;
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}
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bool useHVXV60Ops() const {
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return HexagonHVXVersion >= Hexagon::ArchEnum::V60;
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}
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bool useHVXV62Ops() const {
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return HexagonHVXVersion >= Hexagon::ArchEnum::V62;
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}
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bool useHVXV65Ops() const {
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return HexagonHVXVersion >= Hexagon::ArchEnum::V65;
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}
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bool useHVXV66Ops() const {
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return HexagonHVXVersion >= Hexagon::ArchEnum::V66;
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}
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bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
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bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
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bool hasMemNoShuf() const { return HasMemNoShuf; }
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bool hasReservedR19() const { return ReservedR19; }
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bool usePredicatedCalls() const;
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bool noreturnStackElim() const { return NoreturnStackElim; }
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bool useBSBScheduling() const { return UseBSBScheduling; }
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bool enableMachineScheduler() const override;
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// Always use the TargetLowering default scheduler.
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// FIXME: This will use the vliw scheduler which is probably just hurting
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// compiler time and will be removed eventually anyway.
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bool enableMachineSchedDefaultSched() const override { return false; }
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AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
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bool enablePostRAScheduler() const override { return true; }
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bool enableSubRegLiveness() const override;
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const std::string &getCPUString () const { return CPUString; }
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const Hexagon::ArchEnum &getHexagonArchVersion() const {
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return HexagonArchVersion;
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}
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void getPostRAMutations(
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std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
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const override;
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void getSMSMutations(
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std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
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const override;
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/// Enable use of alias analysis during code generation (during MI
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/// scheduling, DAGCombine, etc.).
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bool useAA() const override;
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/// Perform target specific adjustments to the latency of a schedule
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/// dependency.
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void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
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unsigned getVectorLength() const {
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assert(useHVXOps());
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if (useHVX64BOps())
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return 64;
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if (useHVX128BOps())
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return 128;
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llvm_unreachable("Invalid HVX vector length settings");
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}
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ArrayRef<MVT> getHVXElementTypes() const {
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static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
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return makeArrayRef(Types);
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}
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bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const {
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if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
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return false;
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MVT ElemTy = VecTy.getVectorElementType();
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if (!IncludeBool && ElemTy == MVT::i1)
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return false;
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unsigned HwLen = getVectorLength();
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unsigned NumElems = VecTy.getVectorNumElements();
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ArrayRef<MVT> ElemTypes = getHVXElementTypes();
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if (IncludeBool && ElemTy == MVT::i1) {
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// Special case for the v512i1, etc.
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if (8*HwLen == NumElems)
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return true;
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// Boolean HVX vector types are formed from regular HVX vector types
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// by replacing the element type with i1.
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for (MVT T : ElemTypes)
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if (NumElems * T.getSizeInBits() == 8*HwLen)
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return true;
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return false;
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}
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unsigned VecWidth = VecTy.getSizeInBits();
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if (VecWidth != 8*HwLen && VecWidth != 16*HwLen)
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return false;
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return llvm::any_of(ElemTypes, [ElemTy] (MVT T) { return ElemTy == T; });
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}
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unsigned getTypeAlignment(MVT Ty) const {
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if (isHVXVectorType(Ty, true))
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return getVectorLength();
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return Ty.getSizeInBits() / 8;
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}
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unsigned getL1CacheLineSize() const;
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unsigned getL1PrefetchDistance() const;
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private:
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// Helper function responsible for increasing the latency only.
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void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
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const;
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void restoreLatency(SUnit *Src, SUnit *Dst) const;
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void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
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bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
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SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
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