forked from OSchip/llvm-project
609 lines
20 KiB
C++
609 lines
20 KiB
C++
//===- HexagonStoreWidening.cpp -------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Replace sequences of "narrow" stores to adjacent memory locations with
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// a fewer "wide" stores that have the same effect.
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// For example, replace:
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// S4_storeirb_io %100, 0, 0 ; store-immediate-byte
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// S4_storeirb_io %100, 1, 0 ; store-immediate-byte
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// with
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// S4_storeirh_io %100, 0, 0 ; store-immediate-halfword
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// The above is the general idea. The actual cases handled by the code
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// may be a bit more complex.
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// The purpose of this pass is to reduce the number of outstanding stores,
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// or as one could say, "reduce store queue pressure". Also, wide stores
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// mean fewer stores, and since there are only two memory instructions allowed
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// per packet, it also means fewer packets, and ultimately fewer cycles.
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//===---------------------------------------------------------------------===//
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#include "HexagonInstrInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/MemoryLocation.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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#include <vector>
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#define DEBUG_TYPE "hexagon-widen-stores"
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using namespace llvm;
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namespace llvm {
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FunctionPass *createHexagonStoreWidening();
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void initializeHexagonStoreWideningPass(PassRegistry&);
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} // end namespace llvm
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namespace {
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struct HexagonStoreWidening : public MachineFunctionPass {
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const HexagonInstrInfo *TII;
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const HexagonRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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AliasAnalysis *AA;
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MachineFunction *MF;
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public:
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static char ID;
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HexagonStoreWidening() : MachineFunctionPass(ID) {
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initializeHexagonStoreWideningPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "Hexagon Store Widening"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<AAResultsWrapperPass>();
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AU.addPreserved<AAResultsWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static bool handledStoreType(const MachineInstr *MI);
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private:
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static const int MaxWideSize = 4;
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using InstrGroup = std::vector<MachineInstr *>;
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using InstrGroupList = std::vector<InstrGroup>;
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bool instrAliased(InstrGroup &Stores, const MachineMemOperand &MMO);
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bool instrAliased(InstrGroup &Stores, const MachineInstr *MI);
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void createStoreGroup(MachineInstr *BaseStore, InstrGroup::iterator Begin,
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InstrGroup::iterator End, InstrGroup &Group);
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void createStoreGroups(MachineBasicBlock &MBB,
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InstrGroupList &StoreGroups);
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bool processBasicBlock(MachineBasicBlock &MBB);
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bool processStoreGroup(InstrGroup &Group);
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bool selectStores(InstrGroup::iterator Begin, InstrGroup::iterator End,
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InstrGroup &OG, unsigned &TotalSize, unsigned MaxSize);
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bool createWideStores(InstrGroup &OG, InstrGroup &NG, unsigned TotalSize);
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bool replaceStores(InstrGroup &OG, InstrGroup &NG);
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bool storesAreAdjacent(const MachineInstr *S1, const MachineInstr *S2);
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};
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} // end anonymous namespace
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char HexagonStoreWidening::ID = 0;
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INITIALIZE_PASS_BEGIN(HexagonStoreWidening, "hexagon-widen-stores",
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"Hexason Store Widening", false, false)
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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INITIALIZE_PASS_END(HexagonStoreWidening, "hexagon-widen-stores",
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"Hexagon Store Widening", false, false)
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// Some local helper functions...
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static unsigned getBaseAddressRegister(const MachineInstr *MI) {
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const MachineOperand &MO = MI->getOperand(0);
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assert(MO.isReg() && "Expecting register operand");
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return MO.getReg();
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}
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static int64_t getStoreOffset(const MachineInstr *MI) {
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unsigned OpC = MI->getOpcode();
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assert(HexagonStoreWidening::handledStoreType(MI) && "Unhandled opcode");
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switch (OpC) {
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case Hexagon::S4_storeirb_io:
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case Hexagon::S4_storeirh_io:
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case Hexagon::S4_storeiri_io: {
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const MachineOperand &MO = MI->getOperand(1);
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assert(MO.isImm() && "Expecting immediate offset");
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return MO.getImm();
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}
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}
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dbgs() << *MI;
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llvm_unreachable("Store offset calculation missing for a handled opcode");
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return 0;
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}
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static const MachineMemOperand &getStoreTarget(const MachineInstr *MI) {
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assert(!MI->memoperands_empty() && "Expecting memory operands");
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return **MI->memoperands_begin();
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}
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// Filtering function: any stores whose opcodes are not "approved" of by
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// this function will not be subjected to widening.
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inline bool HexagonStoreWidening::handledStoreType(const MachineInstr *MI) {
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// For now, only handle stores of immediate values.
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// Also, reject stores to stack slots.
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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case Hexagon::S4_storeirb_io:
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case Hexagon::S4_storeirh_io:
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case Hexagon::S4_storeiri_io:
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// Base address must be a register. (Implement FI later.)
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return MI->getOperand(0).isReg();
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default:
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return false;
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}
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}
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// Check if the machine memory operand MMO is aliased with any of the
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// stores in the store group Stores.
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bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
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const MachineMemOperand &MMO) {
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if (!MMO.getValue())
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return true;
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MemoryLocation L(MMO.getValue(), MMO.getSize(), MMO.getAAInfo());
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for (auto SI : Stores) {
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const MachineMemOperand &SMO = getStoreTarget(SI);
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if (!SMO.getValue())
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return true;
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MemoryLocation SL(SMO.getValue(), SMO.getSize(), SMO.getAAInfo());
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if (AA->alias(L, SL))
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return true;
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}
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return false;
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}
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// Check if the machine instruction MI accesses any storage aliased with
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// any store in the group Stores.
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bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
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const MachineInstr *MI) {
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for (auto &I : MI->memoperands())
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if (instrAliased(Stores, *I))
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return true;
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return false;
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}
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// Inspect a machine basic block, and generate store groups out of stores
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// encountered in the block.
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//
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// A store group is a group of stores that use the same base register,
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// and which can be reordered within that group without altering the
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// semantics of the program. A single store group could be widened as
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// a whole, if there existed a single store instruction with the same
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// semantics as the entire group. In many cases, a single store group
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// may need more than one wide store.
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void HexagonStoreWidening::createStoreGroups(MachineBasicBlock &MBB,
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InstrGroupList &StoreGroups) {
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InstrGroup AllInsns;
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// Copy all instruction pointers from the basic block to a temporary
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// list. This will allow operating on the list, and modifying its
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// elements without affecting the basic block.
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for (auto &I : MBB)
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AllInsns.push_back(&I);
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// Traverse all instructions in the AllInsns list, and if we encounter
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// a store, then try to create a store group starting at that instruction
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// i.e. a sequence of independent stores that can be widened.
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for (auto I = AllInsns.begin(), E = AllInsns.end(); I != E; ++I) {
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MachineInstr *MI = *I;
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// Skip null pointers (processed instructions).
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if (!MI || !handledStoreType(MI))
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continue;
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// Found a store. Try to create a store group.
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InstrGroup G;
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createStoreGroup(MI, I+1, E, G);
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if (G.size() > 1)
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StoreGroups.push_back(G);
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}
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}
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// Create a single store group. The stores need to be independent between
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// themselves, and also there cannot be other instructions between them
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// that could read or modify storage being stored into.
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void HexagonStoreWidening::createStoreGroup(MachineInstr *BaseStore,
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InstrGroup::iterator Begin, InstrGroup::iterator End, InstrGroup &Group) {
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assert(handledStoreType(BaseStore) && "Unexpected instruction");
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unsigned BaseReg = getBaseAddressRegister(BaseStore);
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InstrGroup Other;
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Group.push_back(BaseStore);
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for (auto I = Begin; I != End; ++I) {
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MachineInstr *MI = *I;
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if (!MI)
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continue;
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if (handledStoreType(MI)) {
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// If this store instruction is aliased with anything already in the
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// group, terminate the group now.
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if (instrAliased(Group, getStoreTarget(MI)))
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return;
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// If this store is aliased to any of the memory instructions we have
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// seen so far (that are not a part of this group), terminate the group.
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if (instrAliased(Other, getStoreTarget(MI)))
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return;
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unsigned BR = getBaseAddressRegister(MI);
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if (BR == BaseReg) {
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Group.push_back(MI);
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*I = nullptr;
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continue;
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}
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}
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// Assume calls are aliased to everything.
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if (MI->isCall() || MI->hasUnmodeledSideEffects())
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return;
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if (MI->mayLoadOrStore()) {
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if (MI->hasOrderedMemoryRef() || instrAliased(Group, MI))
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return;
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Other.push_back(MI);
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}
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} // for
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}
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// Check if store instructions S1 and S2 are adjacent. More precisely,
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// S2 has to access memory immediately following that accessed by S1.
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bool HexagonStoreWidening::storesAreAdjacent(const MachineInstr *S1,
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const MachineInstr *S2) {
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if (!handledStoreType(S1) || !handledStoreType(S2))
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return false;
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const MachineMemOperand &S1MO = getStoreTarget(S1);
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// Currently only handling immediate stores.
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int Off1 = S1->getOperand(1).getImm();
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int Off2 = S2->getOperand(1).getImm();
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return (Off1 >= 0) ? Off1+S1MO.getSize() == unsigned(Off2)
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: int(Off1+S1MO.getSize()) == Off2;
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}
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/// Given a sequence of adjacent stores, and a maximum size of a single wide
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/// store, pick a group of stores that can be replaced by a single store
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/// of size not exceeding MaxSize. The selected sequence will be recorded
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/// in OG ("old group" of instructions).
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/// OG should be empty on entry, and should be left empty if the function
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/// fails.
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bool HexagonStoreWidening::selectStores(InstrGroup::iterator Begin,
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InstrGroup::iterator End, InstrGroup &OG, unsigned &TotalSize,
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unsigned MaxSize) {
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assert(Begin != End && "No instructions to analyze");
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assert(OG.empty() && "Old group not empty on entry");
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if (std::distance(Begin, End) <= 1)
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return false;
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MachineInstr *FirstMI = *Begin;
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assert(!FirstMI->memoperands_empty() && "Expecting some memory operands");
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const MachineMemOperand &FirstMMO = getStoreTarget(FirstMI);
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unsigned Alignment = FirstMMO.getAlignment();
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unsigned SizeAccum = FirstMMO.getSize();
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unsigned FirstOffset = getStoreOffset(FirstMI);
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// The initial value of SizeAccum should always be a power of 2.
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assert(isPowerOf2_32(SizeAccum) && "First store size not a power of 2");
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// If the size of the first store equals to or exceeds the limit, do nothing.
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if (SizeAccum >= MaxSize)
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return false;
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// If the size of the first store is greater than or equal to the address
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// stored to, then the store cannot be made any wider.
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if (SizeAccum >= Alignment)
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return false;
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// The offset of a store will put restrictions on how wide the store can be.
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// Offsets in stores of size 2^n bytes need to have the n lowest bits be 0.
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// If the first store already exhausts the offset limits, quit. Test this
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// by checking if the next wider size would exceed the limit.
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if ((2*SizeAccum-1) & FirstOffset)
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return false;
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OG.push_back(FirstMI);
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MachineInstr *S1 = FirstMI;
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// Pow2Num will be the largest number of elements in OG such that the sum
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// of sizes of stores 0...Pow2Num-1 will be a power of 2.
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unsigned Pow2Num = 1;
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unsigned Pow2Size = SizeAccum;
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// Be greedy: keep accumulating stores as long as they are to adjacent
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// memory locations, and as long as the total number of bytes stored
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// does not exceed the limit (MaxSize).
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// Keep track of when the total size covered is a power of 2, since
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// this is a size a single store can cover.
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for (InstrGroup::iterator I = Begin + 1; I != End; ++I) {
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MachineInstr *S2 = *I;
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// Stores are sorted, so if S1 and S2 are not adjacent, there won't be
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// any other store to fill the "hole".
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if (!storesAreAdjacent(S1, S2))
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break;
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unsigned S2Size = getStoreTarget(S2).getSize();
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if (SizeAccum + S2Size > std::min(MaxSize, Alignment))
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break;
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OG.push_back(S2);
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SizeAccum += S2Size;
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if (isPowerOf2_32(SizeAccum)) {
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Pow2Num = OG.size();
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Pow2Size = SizeAccum;
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}
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if ((2*Pow2Size-1) & FirstOffset)
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break;
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S1 = S2;
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}
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// The stores don't add up to anything that can be widened. Clean up.
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if (Pow2Num <= 1) {
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OG.clear();
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return false;
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}
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// Only leave the stored being widened.
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OG.resize(Pow2Num);
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TotalSize = Pow2Size;
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return true;
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}
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/// Given an "old group" OG of stores, create a "new group" NG of instructions
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/// to replace them. Ideally, NG would only have a single instruction in it,
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/// but that may only be possible for store-immediate.
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bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG,
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unsigned TotalSize) {
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// XXX Current limitations:
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// - only expect stores of immediate values in OG,
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// - only handle a TotalSize of up to 4.
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if (TotalSize > 4)
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return false;
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unsigned Acc = 0; // Value accumulator.
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unsigned Shift = 0;
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for (InstrGroup::iterator I = OG.begin(), E = OG.end(); I != E; ++I) {
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MachineInstr *MI = *I;
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const MachineMemOperand &MMO = getStoreTarget(MI);
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MachineOperand &SO = MI->getOperand(2); // Source.
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assert(SO.isImm() && "Expecting an immediate operand");
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unsigned NBits = MMO.getSize()*8;
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unsigned Mask = (0xFFFFFFFFU >> (32-NBits));
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unsigned Val = (SO.getImm() & Mask) << Shift;
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Acc |= Val;
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Shift += NBits;
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}
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MachineInstr *FirstSt = OG.front();
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DebugLoc DL = OG.back()->getDebugLoc();
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const MachineMemOperand &OldM = getStoreTarget(FirstSt);
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MachineMemOperand *NewM =
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MF->getMachineMemOperand(OldM.getPointerInfo(), OldM.getFlags(),
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TotalSize, OldM.getAlignment(),
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OldM.getAAInfo());
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if (Acc < 0x10000) {
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// Create mem[hw] = #Acc
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unsigned WOpc = (TotalSize == 2) ? Hexagon::S4_storeirh_io :
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(TotalSize == 4) ? Hexagon::S4_storeiri_io : 0;
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assert(WOpc && "Unexpected size");
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int Val = (TotalSize == 2) ? int16_t(Acc) : int(Acc);
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const MCInstrDesc &StD = TII->get(WOpc);
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MachineOperand &MR = FirstSt->getOperand(0);
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int64_t Off = FirstSt->getOperand(1).getImm();
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MachineInstr *StI =
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BuildMI(*MF, DL, StD)
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.addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
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.addImm(Off)
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.addImm(Val);
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StI->addMemOperand(*MF, NewM);
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NG.push_back(StI);
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} else {
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// Create vreg = A2_tfrsi #Acc; mem[hw] = vreg
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const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi);
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const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF);
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Register VReg = MF->getRegInfo().createVirtualRegister(RC);
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MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg)
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.addImm(int(Acc));
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NG.push_back(TfrI);
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unsigned WOpc = (TotalSize == 2) ? Hexagon::S2_storerh_io :
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(TotalSize == 4) ? Hexagon::S2_storeri_io : 0;
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assert(WOpc && "Unexpected size");
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const MCInstrDesc &StD = TII->get(WOpc);
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MachineOperand &MR = FirstSt->getOperand(0);
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int64_t Off = FirstSt->getOperand(1).getImm();
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MachineInstr *StI =
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BuildMI(*MF, DL, StD)
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.addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
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.addImm(Off)
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.addReg(VReg, RegState::Kill);
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StI->addMemOperand(*MF, NewM);
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NG.push_back(StI);
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}
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return true;
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}
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// Replace instructions from the old group OG with instructions from the
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// new group NG. Conceptually, remove all instructions in OG, and then
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// insert all instructions in NG, starting at where the first instruction
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// from OG was (in the order in which they appeared in the basic block).
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// (The ordering in OG does not have to match the order in the basic block.)
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bool HexagonStoreWidening::replaceStores(InstrGroup &OG, InstrGroup &NG) {
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LLVM_DEBUG({
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dbgs() << "Replacing:\n";
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for (auto I : OG)
|
|
dbgs() << " " << *I;
|
|
dbgs() << "with\n";
|
|
for (auto I : NG)
|
|
dbgs() << " " << *I;
|
|
});
|
|
|
|
MachineBasicBlock *MBB = OG.back()->getParent();
|
|
MachineBasicBlock::iterator InsertAt = MBB->end();
|
|
|
|
// Need to establish the insertion point. The best one is right before
|
|
// the first store in the OG, but in the order in which the stores occur
|
|
// in the program list. Since the ordering in OG does not correspond
|
|
// to the order in the program list, we need to do some work to find
|
|
// the insertion point.
|
|
|
|
// Create a set of all instructions in OG (for quick lookup).
|
|
SmallPtrSet<MachineInstr*, 4> InstrSet;
|
|
for (auto I : OG)
|
|
InstrSet.insert(I);
|
|
|
|
// Traverse the block, until we hit an instruction from OG.
|
|
for (auto &I : *MBB) {
|
|
if (InstrSet.count(&I)) {
|
|
InsertAt = I;
|
|
break;
|
|
}
|
|
}
|
|
|
|
assert((InsertAt != MBB->end()) && "Cannot locate any store from the group");
|
|
|
|
bool AtBBStart = false;
|
|
|
|
// InsertAt points at the first instruction that will be removed. We need
|
|
// to move it out of the way, so it remains valid after removing all the
|
|
// old stores, and so we are able to recover it back to the proper insertion
|
|
// position.
|
|
if (InsertAt != MBB->begin())
|
|
--InsertAt;
|
|
else
|
|
AtBBStart = true;
|
|
|
|
for (auto I : OG)
|
|
I->eraseFromParent();
|
|
|
|
if (!AtBBStart)
|
|
++InsertAt;
|
|
else
|
|
InsertAt = MBB->begin();
|
|
|
|
for (auto I : NG)
|
|
MBB->insert(InsertAt, I);
|
|
|
|
return true;
|
|
}
|
|
|
|
// Break up the group into smaller groups, each of which can be replaced by
|
|
// a single wide store. Widen each such smaller group and replace the old
|
|
// instructions with the widened ones.
|
|
bool HexagonStoreWidening::processStoreGroup(InstrGroup &Group) {
|
|
bool Changed = false;
|
|
InstrGroup::iterator I = Group.begin(), E = Group.end();
|
|
InstrGroup OG, NG; // Old and new groups.
|
|
unsigned CollectedSize;
|
|
|
|
while (I != E) {
|
|
OG.clear();
|
|
NG.clear();
|
|
|
|
bool Succ = selectStores(I++, E, OG, CollectedSize, MaxWideSize) &&
|
|
createWideStores(OG, NG, CollectedSize) &&
|
|
replaceStores(OG, NG);
|
|
if (!Succ)
|
|
continue;
|
|
|
|
assert(OG.size() > 1 && "Created invalid group");
|
|
assert(distance(I, E)+1 >= int(OG.size()) && "Too many elements");
|
|
I += OG.size()-1;
|
|
|
|
Changed = true;
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
// Process a single basic block: create the store groups, and replace them
|
|
// with the widened stores, if possible. Processing of each basic block
|
|
// is independent from processing of any other basic block. This transfor-
|
|
// mation could be stopped after having processed any basic block without
|
|
// any ill effects (other than not having performed widening in the unpro-
|
|
// cessed blocks). Also, the basic blocks can be processed in any order.
|
|
bool HexagonStoreWidening::processBasicBlock(MachineBasicBlock &MBB) {
|
|
InstrGroupList SGs;
|
|
bool Changed = false;
|
|
|
|
createStoreGroups(MBB, SGs);
|
|
|
|
auto Less = [] (const MachineInstr *A, const MachineInstr *B) -> bool {
|
|
return getStoreOffset(A) < getStoreOffset(B);
|
|
};
|
|
for (auto &G : SGs) {
|
|
assert(G.size() > 1 && "Store group with fewer than 2 elements");
|
|
llvm::sort(G, Less);
|
|
|
|
Changed |= processStoreGroup(G);
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
bool HexagonStoreWidening::runOnMachineFunction(MachineFunction &MFn) {
|
|
if (skipFunction(MFn.getFunction()))
|
|
return false;
|
|
|
|
MF = &MFn;
|
|
auto &ST = MFn.getSubtarget<HexagonSubtarget>();
|
|
TII = ST.getInstrInfo();
|
|
TRI = ST.getRegisterInfo();
|
|
MRI = &MFn.getRegInfo();
|
|
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
|
|
|
|
bool Changed = false;
|
|
|
|
for (auto &B : MFn)
|
|
Changed |= processBasicBlock(B);
|
|
|
|
return Changed;
|
|
}
|
|
|
|
FunctionPass *llvm::createHexagonStoreWidening() {
|
|
return new HexagonStoreWidening();
|
|
}
|