Matt Arsenault 3c2a7bd286 AMDGPU: Remove code to handle tied si_else operands ... This has not used tied operands for a long time.		2020-09-03 19:46:05 -04:00
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AArch64	[SVE] Don't reorder subvector/binop sequences when the resulting binop is not legal.	2020-09-02 11:01:33 +01:00
AMDGPU	AMDGPU: Remove code to handle tied si_else operands	2020-09-03 19:46:05 -04:00
ARC	[ARC] Update brcc test.	2020-08-28 17:07:25 -07:00
ARM	Revert "[ARM] Register pressure with -mthumb forces register reload before each call"	2020-09-01 07:39:54 +01:00
AVR	…
BPF	BPF: add a SimplifyCFG IR pass during generic Scalar/IPO optimization	2020-08-06 13:16:00 -07:00
Generic	[Tests] Be consistent w/definition of statepoint-example	2020-08-14 20:45:48 -07:00
Hexagon	[Hexagon] Fix perfect shuffle generation for single vectors	2020-08-30 06:43:16 -05:00
Inputs	…
Lanai	…
MIR	[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)	2020-09-03 16:13:09 -04:00
MSP430	…
Mips	GlobalISel: Add generic instructions for memory intrinsics	2020-08-26 20:08:45 -04:00
NVPTX	[NVPTX] Fix typo in lit test	2020-08-17 16:02:11 -04:00
PowerPC	[PowerPC] Fix missing TLS symbol type.	2020-09-03 05:57:04 -05:00
RISCV	[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move	2020-08-27 10:32:22 +01:00
SPARC	…
SystemZ	Revert "[BPI] Improve static heuristics for integer comparisons"	2020-08-17 20:44:33 +02:00
Thumb	…
Thumb2	[ARM] Extra predicate load tests. NFC	2020-09-03 17:52:37 +01:00
VE	[VE] Support f128	2020-08-17 17:26:52 +09:00
WebAssembly	[SelectionDAG] Handle non-power-of-2 bitwidths in expandROT	2020-08-26 09:20:46 +01:00
WinCFGuard	…
WinEH	…
X86	[X86][SSE] Fold select(X > -1, A, B) -> select(0 > X, B, A) (PR47404)	2020-09-03 13:02:08 +01:00
XCore	…