llvm-project/bolt/lib
Vladislav Khmelevsky e900f0584e [BOLT] Fix AARCH64 registers aliasing
The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7.
Using the downwards propagation this register will become a super
register for all X0..X7 and its super registers which is not right. This
patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator.

Vladislav Khmelevsky,
Advanced Software Technology Lab, Huawei

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D117394
2022-01-28 01:24:35 +03:00
..
Core [BOLT] Fix AARCH64 registers aliasing 2022-01-28 01:24:35 +03:00
Passes [BOLT][NFC] Reduce includes with include-what-you-use 2022-01-21 12:05:47 -08:00
Profile [BOLT][NFC] Expand auto types pt.2 2022-01-21 12:02:57 -08:00
Rewrite [BOLT][DWARF] Fix gdb index section 2022-01-27 12:07:58 -08:00
RuntimeLibs [BOLT][NFC] Fix braces usage in the rest of the codebase 2021-12-28 18:43:53 -08:00
Target [BOLT][NFC] Move Offset annotation to Group 1 2022-01-18 13:24:50 -08:00
Utils [BOLT] Prepare BOLT for unit-testing 2022-01-27 00:22:13 +03:00
CMakeLists.txt Rebase: [NFC] Refactor sources to be buildable in shared mode 2021-10-08 11:47:10 -07:00