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Farhana Aleen ce095c564a [AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions. 
Summary: Promote constant offset to immediate by recomputing the relative 13bit offset from nearby instructions.
 E.g.
  s_movk_i32 s0, 0x1800
  v_add_co_u32_e32 v0, vcc, s0, v2
  v_addc_co_u32_e32 v1, vcc, 0, v6, vcc

  s_movk_i32 s0, 0x1000
  v_add_co_u32_e32 v5, vcc, s0, v2
  v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
  global_load_dwordx2 v[5:6], v[5:6], off
  global_load_dwordx2 v[0:1], v[0:1], off
  =>
  s_movk_i32 s0, 0x1000
  v_add_co_u32_e32 v5, vcc, s0, v2
  v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
  global_load_dwordx2 v[5:6], v[5:6], off
  global_load_dwordx2 v[0:1], v[5:6], off offset:2048

Author: FarhanaAleen

Reviewed By: arsenm, rampitec

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D55539

llvm-svn: 349196
 		2018-12-14 21:13:14 +00:00
..
GlobalISel AMDGPU/GlobalISel: Legalize/regbankselect block_addr 2018-12-13 20:34:15 +00:00
32-bit-local-address-space.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
InlineAsmCrash.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
README
…
add-debug.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
add.i16.ll Allow target to decide when to cluster loads/stores in misched 2017-09-13 22:20:47 +00:00
add.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
add.v2i16.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
add3.ll AMDGPU: Generate VALU ThreeOp Integer instructions 2018-12-06 14:33:40 +00:00
add_i1.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
add_i64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
add_i128.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
add_shl.ll AMDGPU: Generate VALU ThreeOp Integer instructions 2018-12-06 14:33:40 +00:00
addrspacecast-captured.ll AMDGPU: Fix using old address spaces in some tests 2018-12-05 17:34:59 +00:00
addrspacecast-constantexpr.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
addrspacecast.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
adjust-writemask-invalid-copy.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
alignbit-pat.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
always-uniform.ll DivergencyAnalysis patch for review 2017-06-15 19:33:10 +00:00
amdgcn.bitcast.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
amdgcn.private-memory.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
amdgpu-alias-analysis.ll Allow subclassing ExternalAA 2018-11-07 20:26:42 +00:00
amdgpu-codegenprepare-fdiv.ll [AMDGPU] Always use rcp + mul with fast math 2017-07-06 20:34:21 +00:00
amdgpu-codegenprepare-i16-to-i32.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-codegenprepare-idiv.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-inline.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
amdgpu-shader-calling-convention.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
amdgpu.private-memory.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
amdgpu.work-item-intrinsics.deprecated.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
amdhsa-trap-num-sgprs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
amdpal-cs.ll AMDGPU/NFC: Minor clean ups in PAL metadata 2017-10-11 22:41:09 +00:00
amdpal-es.ll AMDGPU/NFC: Minor clean ups in PAL metadata 2017-10-11 22:41:09 +00:00
amdpal-gs.ll AMDGPU/NFC: Minor clean ups in PAL metadata 2017-10-11 22:41:09 +00:00
amdpal-hs.ll AMDGPU/NFC: Minor clean ups in PAL metadata 2017-10-11 22:41:09 +00:00
amdpal-ls.ll AMDGPU/NFC: Minor clean ups in PAL metadata 2017-10-11 22:41:09 +00:00
amdpal-ps.ll AMDGPU/NFC: Minor clean ups in PAL metadata 2017-10-11 22:41:09 +00:00
amdpal-psenable.ll [AMDGPU] For amdpal, widen interpolation mode workaround 2017-10-12 16:16:41 +00:00
amdpal-vs.ll AMDGPU/NFC: Minor clean ups in PAL metadata 2017-10-11 22:41:09 +00:00
amdpal.ll [AMDGPU] For OS type AMDPAL, fixed scratch on compute shader 2018-04-10 11:25:15 +00:00
amdpal_scratch_mergedshader.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
and-gcn.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
and.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
and_or.ll AMDGPU: Generate VALU ThreeOp Integer instructions 2018-12-06 14:33:40 +00:00
andorbitset.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
andorn2.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
andorxorinvimm.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
annotate-kernel-features-hsa-call.ll Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute 2018-12-13 21:23:12 +00:00
annotate-kernel-features-hsa.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
annotate-kernel-features.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
anonymous-gv.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
any_extend_vector_inreg.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
anyext.ll AMDGPU: Set v2i32 any_extend to expand 2017-10-05 17:38:30 +00:00
array-ptr-calc-i32.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
array-ptr-calc-i64.ll AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt 2017-11-13 22:55:05 +00:00
ashr.v2i16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
atomic_cmp_swap_local.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
atomic_load_add.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_load_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomic_load_sub.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_buffer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_global_pointer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_local_pointer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_pixelshader.ll [AMDGPU] Fix the new atomic optimizer in pixel shaders. 2018-11-05 12:04:48 +00:00
atomic_optimizations_raw_buffer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_struct_buffer.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_store_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomicrmw-nand.ll AMDGPU: Expand atomicrmw nand in IR 2018-10-02 03:50:56 +00:00
attr-amdgpu-flat-work-group-size-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
attr-amdgpu-flat-work-group-size.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
attr-amdgpu-num-sgpr-spill-to-smem.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
attr-amdgpu-num-sgpr.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
attr-amdgpu-num-vgpr.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
attr-amdgpu-waves-per-eu.ll AMDGPU: Fix amdgpu-flat-work-group-size/amdgpu-waves-per-eu check 2017-07-16 19:38:47 +00:00
attr-unparseable.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
barrier-elimination.ll [AMDGPU] Eliminate barrier if workgroup size is not greater than wavefront size 2017-04-06 16:48:30 +00:00
basic-branch.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
basic-call-return.ll AMDGPU: Fix register name format in tests 2018-03-27 18:39:42 +00:00
basic-loop.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
bfe-combine.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
bfe-patterns.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
bfe_uint.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
bfi_int.ll AMDGPU: Scalarize vector argument types to calls 2018-07-31 19:05:14 +00:00
bfm.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
big_alu.ll
…
bitcast-constant-to-vector.ll AMDGPU: Fix assertion with bitcast from i64 constant to v4i16 2018-11-02 02:43:55 +00:00
bitcast-vector-extract.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
bitreverse-inline-immediates.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
bitreverse.ll DAG: Fix not truncating when promoting bswap/bitreverse 2018-01-31 23:54:16 +00:00
br_cc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
branch-condition-and.ll [AMDGPU] Eliminate no effect instructions before s_endpgm 2017-08-16 04:43:49 +00:00
branch-relax-bundle.ll AMDGPU: Fix not accounting for instruction size in bundles 2017-10-04 22:59:12 +00:00
branch-relax-spill.ll AMDGPU: Use scavengeRegisterBackwards 2018-10-30 01:33:14 +00:00
branch-relaxation.ll [MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM 2018-12-05 03:41:26 +00:00
branch-uniformity.ll
…
break-smem-soft-clauses.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
break-vmem-soft-clauses.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bswap.ll DAG: Fix not truncating when promoting bswap/bitreverse 2018-01-31 23:54:16 +00:00
buffer-schedule.ll [AMDGPU] stop buffer_store being moved illegally 2018-02-20 10:03:38 +00:00
bug-vopc-commute.ll AMDGPU: Remove SITypeRewriter 2017-06-28 21:38:50 +00:00
build-vector-insert-elt-infloop.ll [LICM] Use ICFLoopSafetyInfo in LICM 2018-11-06 02:44:49 +00:00
build-vector-packed-partial-undef.ll AMDGPU: Fix packing undef parts of build_vector 2018-08-12 08:42:46 +00:00
build_vector.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
byval-frame-setup.ll AMDGPU: Cleanup / relax tests for future changes 2018-11-26 17:17:07 +00:00
call-argument-types.ll Bias physical register immediate assignments 2018-11-14 21:11:53 +00:00
call-constexpr.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
call-encoding.ll AMDGPU: Remove error on calls for amdgcn 2017-08-03 23:24:05 +00:00
call-graph-register-usage.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
call-preserved-registers.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
call-return-types.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
call_fs.ll
…
callee-frame-setup.ll AMDGPU: Increase default stack alignment 2018-03-29 20:22:04 +00:00
callee-special-input-sgprs.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
callee-special-input-vgprs.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
calling-conventions.ll AMDGPU: Partially fix handling of packed amdgpu_ps arguments 2018-08-01 19:57:34 +00:00
captured-frame-index.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
cayman-loop-bug.ll
…
cf-loop-on-constant.ll AMDGPU: Try a lot harder to emit scalar loads 2018-06-07 09:54:49 +00:00
cf-stack-bug.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
cf_end.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
cgp-addressing-modes-flat.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
cgp-addressing-modes.ll AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
cgp-bitfield-extract.ll [DAGCombiner] re-enable truncation of binops 2018-12-08 16:07:38 +00:00
clamp-modifier.ll AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
clamp-omod-special-case.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
clamp.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
cluster-flat-loads-postra.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
cluster-flat-loads.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
cndmask-no-def-vcc.ll [DAG] add undef simplifications for select nodes 2018-11-18 17:36:23 +00:00
coalescer-extend-pruned-subrange.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-identical-values-undef.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-subranges-another-copymi-not-live.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-subranges-another-prune-error.mir AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
coalescer-subreg-join.mir AMDGPU: Turn D16 for MIMG instructions into a regular operand 2018-06-21 13:36:01 +00:00
coalescer-subregjoin-fullcopy.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-with-subregs-bad-identical.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer_distribute.ll AMDGPU: Don't use spir_kernel in a test 2018-07-05 17:01:29 +00:00
coalescer_remat.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
coalescing-with-subregs-in-loop-bug.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
code-object-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
codegen-prepare-addrmode-sext.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
collapse-endcf.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
combine-and-sext-bool.ll [AMDGPU] Combine and x, (sext cc from i1) => select cc, x, 0 2017-06-27 18:25:26 +00:00
combine-cond-add-sub.ll [AMDGPU] A trivial fix for a buildbot failure caused by "commit 224a839fcbbead221f872cd32a1dd0c308d37299". 2018-05-02 18:16:39 +00:00
combine-ftrunc.ll Eliminate ftrunc if source is know to be rounded 2017-10-02 16:57:07 +00:00
combine_vloads.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
comdat.ll [AMDGPU] Fix compilation failure when IR contains comdat 2018-05-11 20:40:14 +00:00
commute-compares.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
commute-shifts.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
commute_modifiers.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
complex-folding.ll
…
computeKnownBits-scalar-to-vector-crash.ll [SelectionDAG] Don't pass on DemandedElts when handling SCALAR_TO_VECTOR 2018-12-07 09:18:44 +00:00
concat_vectors.ll DAG: Fix creating concat_vectors with illegal type 2018-06-15 12:09:15 +00:00
constant-address-space-32bit.ll AMDGPU: Handle 32-bit address wraparounds for SMRD opcodes 2018-08-29 20:03:00 +00:00
constant-fold-imm-immreg.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
constant-fold-mi-operands.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
control-flow-fastregalloc.ll RegAllocFast: Leave unassigned virtreg entries in map 2018-11-07 06:57:03 +00:00
control-flow-optnone.ll Revert "StructurizeCFG: Test for branch divergence correctly" 2018-02-24 17:29:09 +00:00
convergent-inlineasm.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
copy-illegal-type.ll [DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target. 2018-08-28 03:47:20 +00:00
copy-to-reg.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
couldnt-join-subrange-3.mir AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
cross-block-use-is-not-abi-copy.ll DAG: Don't use ABI copies in some contexts 2018-08-30 05:49:28 +00:00
ctlz.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
ctlz_zero_undef.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop64.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
cttz_zero_undef.ll [DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero 2018-02-06 23:54:37 +00:00
cube.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
cvt_f32_ubyte.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
cvt_flr_i32_f32.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
cvt_rpi_i32_f32.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
dag-divergence.ll AMDGPU: Fix DAG divergence not reporting flat loads 2018-09-04 18:58:19 +00:00
dagcomb-shuffle-vecextend-non2.ll [DAGCombine] Fix for shuffle to vector extend for non power 2 vectors 2017-10-10 12:45:45 +00:00
dagcombine-reassociate-bug.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
dagcombine-select.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
dagcombine-setcc-select.ll [AMDGPU] Disable DAG combine at -O0 2018-11-27 15:13:37 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
dead_copy.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
debug-value.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
debug-value2.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
debug.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
debugger-emit-prologue.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
debugger-insert-nops.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
default-fp-mode.ll AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
detect-dead-lanes.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
directive-amdgcn-target.ll AMDGPU: Add sram-ecc feature 2018-11-05 22:44:19 +00:00
disconnected-predset-break-bug.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
div_i128.ll AMDGPU: Error more gracefully on libcalls 2018-08-08 16:58:39 +00:00
diverge-extra-formal-args.ll [AMDGPU] Fix issues for backend divergence tracking 2018-04-18 13:53:31 +00:00
diverge-interp-mov-lower.ll [AMDGPU] Fix issues for backend divergence tracking 2018-04-18 13:53:31 +00:00
diverge-switch-default.ll [AMDGPU] restore r342722 which was reverted with r342743 2018-09-25 09:39:21 +00:00
divrem24-assume.ll [AMDGPU] Use AssumptionCacheTracker in the divrem32 expansion 2018-07-25 17:02:11 +00:00
dpp_combine.ll [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 2018-11-30 14:21:56 +00:00
dpp_combine_subregs.mir [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 2018-11-30 14:21:56 +00:00
drop-mem-operand-move-smrd.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
ds-combine-large-stride.ll [AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64 2018-01-22 21:46:43 +00:00
ds-negative-offset-addressing-mode-loop.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
ds-sub-offset.ll AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
ds_read2.ll AMDGPU: Track physreg uses in SILoadStoreOptimizer 2018-02-23 10:45:56 +00:00
ds_read2_offset_order.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
ds_read2_superreg.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
ds_read2st64.ll AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
ds_write2.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
ds_write2st64.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
dynamic_stackalloc.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
early-if-convert-cost.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
early-if-convert.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
early-inline-alias.ll [AMDGPU] Run always inliner early in opt 2017-03-20 18:06:45 +00:00
early-inline.ll Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
elf-header-flags-mach.ll AMDGPU: Add sram-ecc feature 2018-11-05 22:44:19 +00:00
elf-header-flags-sram-ecc.ll AMDGPU: Add sram-ecc feature 2018-11-05 22:44:19 +00:00
elf-header-flags-xnack.ll AMDGPU: Bring elf flags in sync with the spec 2018-02-16 22:33:59 +00:00
elf-header-osabi.ll AMDGPU: Bring elf flags in sync with the spec 2018-02-16 22:33:59 +00:00
elf-notes.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
elf.ll AMDGPU: Correctly set EI_OSABI based on the os 2017-10-04 22:44:13 +00:00
elf.metadata.ll [AMDGPU] Set metadata access for explicit section 2018-12-12 11:20:04 +00:00
elf.r600.ll AMDGPU: Correctly set EI_OSABI based on the os 2017-10-04 22:44:13 +00:00
else.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
empty-function.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
enable-no-signed-zeros-fp-math.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
endcf-loop-header.ll AMDGPU: Remove old intrinsic uses 2017-05-17 21:38:21 +00:00
endpgm-dce.mir AMDGPU: Don't delete instructions if S_ENDPGM has implicit uses 2018-08-28 18:55:55 +00:00
enqueue-kernel.ll [AMDGPU] Change enqueue kernel handle type 2018-06-13 17:31:51 +00:00
exceed-max-sgprs.ll AMDGPU: Use correct register names in inline assembly 2017-06-08 19:03:20 +00:00
extend-bit-ops-i16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
extload-align.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extload-private.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
extload.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
extract-lowbits.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
extract-subvector-equal-length.ll [CodeGen] Fix assert in SelectionDAG::computeKnownBits 2018-08-13 18:44:21 +00:00
extract-vector-elt-build-vector-combine.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
extract_vector_dynelt.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
extract_vector_elt-f16.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-f64.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
extract_vector_elt-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
extract_vector_elt-i16.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-i64.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
extractelt-to-trunc.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fabs.f16.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fabs.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
fadd-fma-fmul-combine.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
fadd.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fadd.ll Utilize new SDNode flag functionality to expand current support for fadd 2018-06-18 23:44:59 +00:00
fadd64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fcanonicalize-elimination.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fcanonicalize.f16.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
fcanonicalize.ll AMDGPU: Expand vector canonicalizes 2018-09-18 01:51:33 +00:00
fceil.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fceil64.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
fcmp-cnd.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fcmp-cnde-int-args.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fcmp.f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fcmp.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fcmp64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fconst64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fcopysign.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f32.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fdiv.f16.ll Utilize new SDNode flag functionality to expand current support for fdiv 2018-06-15 20:44:55 +00:00
fdiv.f64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fdiv.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
fdiv32-to-rcp-folding.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
fdot2.ll AMDGPU: Fix V_FMA_F16 selection on GFX9 2018-11-19 21:10:16 +00:00
fence-barrier.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
fexp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ffloor.f64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
ffloor.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fix-vgpr-copies.mir Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
fix-wwm-liveness.mir [AMDGPU] Reworked SIFixWWMLiveness 2018-08-02 23:31:32 +00:00
flat-address-space.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
flat-for-global-subtarget-feature.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
flat-load-clustering.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
flat-scratch-reg.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
flat_atomics.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
flat_atomics_i64.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
floor.ll
…
fma-combine.ll AMDGPU: Fix -enable-var-scope violations 2017-11-12 23:53:44 +00:00
fma.f64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fma.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmad.ll
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fmax.ll
…
fmax3.f64.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax3.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax_legacy.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax_legacy.f64.ll AMDGPU: Cleanup min/max legacy tests 2018-08-12 19:29:53 +00:00
fmax_legacy.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmaxnum.f64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fmaxnum.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmaxnum.r600.ll AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests 2018-07-31 20:38:42 +00:00
fmed3.ll AMDGPU: Don't form fmed3 if it will require materialization 2018-09-18 02:34:54 +00:00
fmin.ll
…
fmin3.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmin_fmax_legacy.amdgcn.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmin_legacy.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmin_legacy.f64.ll AMDGPU: Cleanup min/max legacy tests 2018-08-12 19:29:53 +00:00
fmin_legacy.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.f64.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.r600.ll AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests 2018-07-31 20:38:42 +00:00
fmul-2-combine-multi-use.ll DAG: Enhance isKnownNeverNaN 2018-08-03 18:27:52 +00:00
fmul.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmul.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fmul64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fmuladd.f16.ll [AMDGPU] Removed redundant run lines for fmuladd.f16 test. NFC. 2018-02-20 19:19:56 +00:00
fmuladd.f32.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
fmuladd.f64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fmuladd.v2f16.ll [AMDGPU] Enabled v2.16 literals for VOP3P 2018-04-17 23:09:05 +00:00
fnearbyint.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fneg-combines.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fneg-combines.si.ll AMDGPU: Address todo for handling 1/(2 pi) 2018-08-15 21:03:55 +00:00
fneg-fabs.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg-fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg-fabs.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
fneg.f16.ll AMDGPU: Use scalar operations for f16 fabs/fneg patterns 2018-06-07 10:15:20 +00:00
fneg.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg.ll AMDGPU: Implement hasBitPreservingFPLogic 2017-10-13 21:10:22 +00:00
fold-cndmask.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fold-fmul-to-neg-abs.ll Fold fneg and fabs like multiplications 2017-06-28 20:25:50 +00:00
fold-imm-copy.mir [AMDGPU] Preliminary patch for divergence driven instruction selection. Operands Folding 1. 2018-08-30 13:55:04 +00:00
fold-imm-f16-f32.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fold-immediate-operand-shrink-with-carry.mir MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
fold-immediate-operand-shrink.mir Don't count debug instructions towards neighborhood count 2018-08-30 07:18:19 +00:00
fold-immediate-output-mods.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fold-implicit-operand.mir AMDGPU: Don't crash when trying to fold implicit operands 2018-02-08 01:12:46 +00:00
fold-multiple.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fold-operands-order.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fold-vgpr-copy.mir [AMDGPU] Fold copy (copy vgpr) 2018-09-27 18:55:20 +00:00
force-alwaysinline-lds-global-address-codegen.ll AMDGPU: Always run AMDGPUAlwaysInline 2018-10-03 02:47:25 +00:00
force-alwaysinline-lds-global-address.ll AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
fp-classify.ll AMDGPU: Combine and of seto/setuo and fp_class 2018-08-10 18:58:56 +00:00
fp16_to_fp32.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fp16_to_fp64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fp32_to_fp16.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fp_to_sint.f64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fp_to_sint.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fp_to_uint.f64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fp_to_uint.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fpext-free.ll AMDGPU: Fix V_FMA_F16 selection on GFX9 2018-11-19 21:10:16 +00:00
fpext.f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fpext.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fptosi.f16.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
fptoui.f16.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
fptrunc.f16.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
fptrunc.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
fract.f64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fract.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
frame-index-elimination.ll Bias physical register immediate assignments 2018-11-14 21:11:53 +00:00
frem.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
fsqrt.f64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fsqrt.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
fsub.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fsub.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
fsub64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
ftrunc.f64.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
ftrunc.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
function-args.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
function-returns.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
gep-address-space.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
gfx902-without-xnack.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
global-constant.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
global-directive.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
global-extload-i16.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
global-load-store-atomics.mir [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
global-saddr.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
global-smrd-unknown.ll AMDGPU: Don't use undef in a test 2018-05-08 18:43:34 +00:00
global-variable-relocs.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
global_atomics.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
global_atomics_i64.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
global_smrd.ll AMDGPU: Use GOT PSV since it has an address space now 2018-09-10 02:23:39 +00:00
global_smrd_cfg.ll DivergencyAnalysis patch for review 2017-06-15 19:33:10 +00:00
gv-const-addrspace.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
gv-offset-folding.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
half.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
hazard-buffer-store-v-interp.mir [AMDGPU] Add VALU to V_INTERP Instructions 2018-07-05 12:02:07 +00:00
hazard-inlineasm.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
hazard.mir [AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting 2018-09-10 10:14:48 +00:00
hoist-cond.ll
…
hsa-default-device.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
hsa-fp-mode.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa-func-align.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
hsa-func.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa-globals.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
hsa-group-segment.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
hsa-metadata-deduce-ro-arg-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-deduce-ro-arg.ll AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is not available 2017-12-08 19:22:12 +00:00
hsa-metadata-enqueu-kernel-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-enqueue-kernel.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa-metadata-from-llvm-ir-full-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-from-llvm-ir-full.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa-metadata-hidden-args-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-hidden-args.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa-metadata-images-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-images.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa-metadata-invalid-ocl-version-1-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-invalid-ocl-version-1.ll llvm-readobj: Print AMDGPU note contents 2017-10-14 18:21:42 +00:00
hsa-metadata-invalid-ocl-version-2-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-invalid-ocl-version-2.ll llvm-readobj: Print AMDGPU note contents 2017-10-14 18:21:42 +00:00
hsa-metadata-invalid-ocl-version-3-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-invalid-ocl-version-3.ll llvm-readobj: Print AMDGPU note contents 2017-10-14 18:21:42 +00:00
hsa-metadata-kernel-code-props-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
hsa-metadata-kernel-code-props.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa-metadata-kernel-debug-props.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa-note-no-func.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
hsa.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
huge-private-buffer.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
i1-copy-from-loop.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
i1-copy-implicit-def.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
i1-copy-phi-uniform-branch.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
i1-copy-phi.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
i8-to-double-to-float.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
icmp-select-sete-reverse-args.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
icmp.i16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
icmp64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
idiv-licm.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
idot2.ll AMDGPU: Actually commit re-run of update_llc_test_checks 2018-08-31 15:05:06 +00:00
idot4.ll [AMDGPU] Match signed dot4/8 pattern. 2018-10-04 16:57:37 +00:00
idot8.ll [SelectionDAG] Improve SimplifyDemandedBits to SimplifyDemandedVectorElts simplification 2018-12-01 12:08:55 +00:00
illegal-sgpr-to-vgpr-copy.ll AMDGPU: Use correct register names in inline assembly 2017-06-08 19:03:20 +00:00
image-attributes.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
image-resource-id.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
image-schedule.ll AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
imm.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
imm16.ll AMDGPU: Try a lot harder to emit scalar loads 2018-06-07 09:54:49 +00:00
immv216.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
indirect-addressing-si-gfx9.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
indirect-addressing-si-noopt.ll [AMDGPU] Disable DAG combine at -O0 2018-11-27 15:13:37 +00:00
indirect-addressing-si-pregfx9.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
indirect-addressing-si.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
indirect-private-64.ll AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements 2018-02-16 19:14:17 +00:00
infer-addrpace-pipeline.ll [AMDGPU] Add infer address spaces pass before SROA 2017-06-19 23:17:36 +00:00
infinite-loop-evergreen.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
infinite-loop.ll [MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM 2018-12-05 03:41:26 +00:00
inline-asm.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
inline-attr.ll [AMDGPU] Set fast-math flags on functions given the options 2017-09-29 23:40:19 +00:00
inline-calls.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
inline-constraints.ll [AMDGPU] Inline asm - added i16, half and i128 types support 2018-06-08 16:29:04 +00:00
inlineasm-16.ll [AMDGPU] Inline asm - added i16, half and i128 types support 2018-06-08 16:29:04 +00:00
inlineasm-illegal-type.ll [AMDGPU] Inline asm - added i16, half and i128 types support 2018-06-08 16:29:04 +00:00
inlineasm-packed.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
input-mods.ll
…
insert-skip-from-vcc.mir [AMDGPU] Optimize S_CBRANCH_VCC[N]Z -> S_CBRANCH_EXEC[N]Z 2018-11-12 18:48:17 +00:00
insert-skips-kill-uncond.mir AMDGPU: Add implicit def of SCC to kill and indirect pseudos 2018-06-21 13:36:08 +00:00
insert-waitcnts-callee.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
insert-waitcnts-exp.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
insert_subreg.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
insert_vector_dynelt.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
insert_vector_elt.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
insert_vector_elt.v2i16.ll [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST 2018-11-16 01:13:34 +00:00
insert_vector_elt.v2i16.subtest-nosaddr.ll [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST 2018-11-16 01:13:34 +00:00
insert_vector_elt.v2i16.subtest-saddr.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
inserted-wait-states.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
internalize.ll AMDGPU: Stop forcing internalize at -O0 2018-08-31 06:02:36 +00:00
invalid-addrspacecast.ll AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bit 2018-09-10 11:59:27 +00:00
invalid-alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
invariant-load-no-alias-store.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
invert-br-undef-vcc.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
ipra.ll AMDGPU: Enable IPRA 2017-11-28 23:40:12 +00:00
jump-address.ll [AMDGPU] change test to avoid NaN math 2018-03-19 19:26:22 +00:00
kcache-fold.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
kernarg-stack-alignment.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
kernel-args.ll AMDGPU: Fix offsets for < 4-byte aggregate kernel arguments 2018-12-07 22:12:17 +00:00
kernel-argument-dag-lowering.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
known-never-nan.ll DAG: Handle extract_vector_elt in isKnownNeverNaN 2018-09-03 14:01:03 +00:00
known-never-snan.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
knownbits-recursion.ll [AMDGPU] Testcase for computeKnownBits recursion. NFC. 2017-09-01 22:25:22 +00:00
large-alloca-compute.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
large-alloca-graphics.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
large-constant-initializer.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
large-work-group-promote-alloca.ll AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements 2018-02-16 19:14:17 +00:00
lds-alignment.ll [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
lds-bounds.ll AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI 2018-10-17 15:37:48 +00:00
lds-global-non-entry-func.ll AMDGPU: Error on LDS global address in functions 2018-06-08 08:05:54 +00:00
lds-initializer.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
lds-m0-init-in-loop.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
lds-oqap-crash.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
lds-output-queue.ll [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
lds-size.ll AMDGPU/AMDHSA: Set COMPUTE_PGM_RSRC2:LDS_SIZE to 0 2017-05-05 20:13:55 +00:00
lds-zero-initializer.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
lds_atomic_f32.ll [AMDGPU] fix LDS f32 intrinsics 2018-01-26 11:09:38 +00:00
legalize-fp-load-invariant.ll [AMDGPU] Rename pass "isel" to "amdgpu-isel" 2018-10-03 03:38:22 +00:00
legalizedag-bug-expand-setcc.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
limit-coalesce.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
lit.local.cfg
…
literals.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
liveness.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
llvm.amdgcn.alignb.ll [AMDGPU] Add intrinsics for alignbit and alignbyte instructions 2017-06-09 19:03:00 +00:00
llvm.amdgcn.atomic.dec.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
llvm.amdgcn.atomic.inc.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
llvm.amdgcn.buffer.atomic.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
llvm.amdgcn.buffer.load.format.d16.ll AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature. 2018-02-01 18:41:33 +00:00
llvm.amdgcn.buffer.load.format.ll AMDGPU: Split MUBUF offset into aligned components 2017-10-10 12:22:23 +00:00
llvm.amdgcn.buffer.load.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
llvm.amdgcn.buffer.store.format.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.buffer.store.format.ll [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account. 2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.store.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
llvm.amdgcn.buffer.wbinvl1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.sc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.vol.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.class.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.class.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.cos.f16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.cos.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.cubeid.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.cubema.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.cubesc.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.cubetc.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.cvt.pk.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pk.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pkrtz.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.dispatch.id.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.dispatch.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.div.fixup.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.div.fixup.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.fmas.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
llvm.amdgcn.div.scale.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.ds.bpermute.ll [DAGCombine] (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) 2017-09-14 10:38:30 +00:00
llvm.amdgcn.ds.permute.ll [AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing. 2017-04-12 03:25:12 +00:00
llvm.amdgcn.ds.swizzle.ll [AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests. 2017-06-02 14:19:25 +00:00
llvm.amdgcn.exp.compr.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
llvm.amdgcn.exp.ll AMDGPU: Force skip over s_sendmsg and exp instructions 2018-07-30 09:23:59 +00:00
llvm.amdgcn.fcmp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fdiv.fast.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.fdot2.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.fmad.ftz.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmad.ftz.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmed3.f16.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
llvm.amdgcn.fmed3.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmul.legacy.ll [AMDGPU] Allow SDWA in instructions with immediates and SGPRs 2017-05-30 16:49:24 +00:00
llvm.amdgcn.fract.f16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.fract.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.frexp.exp.f16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.frexp.exp.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.frexp.mant.f16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.frexp.mant.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.groupstaticsize.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.icmp.ll AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16 2018-08-15 21:25:20 +00:00
llvm.amdgcn.image.a16.dim.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.atomic.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.d16.dim.ll AMDGPU: Dimension-aware image intrinsics 2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.dim.ll Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll [AMDGPU] Add support for a16 modifiear for gfx9 2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll AMDGPU: Dimension-aware image intrinsics 2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.gather4.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.gather4.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.getlod.dim.ll AMDGPU: Select MIMG instructions manually in SITargetLowering 2018-06-21 13:36:57 +00:00
llvm.amdgcn.image.load.a16.d16.ll Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
llvm.amdgcn.image.load.a16.ll Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Add support for a16 modifiear for gfx9 2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.sample.d16.dim.ll Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
llvm.amdgcn.image.sample.dim.ll Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
llvm.amdgcn.image.sample.ltolz.ll [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero 2018-08-01 12:12:01 +00:00
llvm.amdgcn.image.sample.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.store.a16.d16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.store.a16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicit.buffer.ptr.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicitarg.ptr.ll [AMDGPU] Avoid using divergent value in mubuf addr64 descriptor 2018-08-02 22:53:57 +00:00
llvm.amdgcn.init.exec.ll AMDGPU: Fix a corner case crash in SIOptimizeExecMasking 2018-04-23 13:05:50 +00:00
llvm.amdgcn.interp.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.kill.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.ldexp.f16.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
llvm.amdgcn.ldexp.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.lerp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.log.clamp.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.mbcnt.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
llvm.amdgcn.mov.dpp.ll run post-RA hazard recognizer pass late 2018-07-16 10:02:41 +00:00
llvm.amdgcn.mqsad.pk.u16.u8.ll [AMDGPU] Eliminate SGPR to VGPR copy when possible 2017-06-20 18:32:42 +00:00
llvm.amdgcn.mqsad.u32.u8.ll AMDGPU: Use correct register names in inline assembly 2017-06-08 19:03:20 +00:00
llvm.amdgcn.msad.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.ps.live.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll [AMDGPU] Eliminate SGPR to VGPR copy when possible 2017-06-20 18:32:42 +00:00
llvm.amdgcn.queue.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.raw.buffer.atomic.ll AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics 2018-10-08 16:53:48 +00:00
llvm.amdgcn.raw.buffer.load.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.ll [AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics 2018-10-03 10:29:43 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.ll [AMDGPU] Allow int types for MUBUF vdata 2018-08-21 11:08:12 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.load.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.store.d16.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.store.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.rcp.f16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.rcp.legacy.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.rcp.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.readfirstlane.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.readlane.ll AMDGPU: Move v_readlane lane select from VGPR to SGPR 2017-04-24 17:17:36 +00:00
llvm.amdgcn.rsq.clamp.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.rsq.f16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.rsq.legacy.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.rsq.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.barrier.ll AMDGPU: Start selecting global instructions 2017-07-29 01:03:53 +00:00
llvm.amdgcn.s.buffer.load.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
llvm.amdgcn.s.dcache.inv.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.inv.vol.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.vol.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.decperflevel.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.getpc.ll Resubmit r303859 with test fixed. 2017-05-26 20:38:26 +00:00
llvm.amdgcn.s.getreg.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.incperflevel.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.memrealtime.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.memtime.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.sleep.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.waitcnt.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.sad.hi.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sbfe.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
llvm.amdgcn.sdot2.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.sdot4.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.sdot8.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.sendmsg.ll AMDGPU: Force skip over s_sendmsg and exp instructions 2018-07-30 09:23:59 +00:00
llvm.amdgcn.set.inactive.ll [AMDGPU] Implement llvm.amdgcn.set.inactive intrinsic 2017-08-04 18:36:54 +00:00
llvm.amdgcn.sffbh.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
llvm.amdgcn.sin.f16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.sin.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.struct.buffer.atomic.ll AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics 2018-10-08 16:53:48 +00:00
llvm.amdgcn.struct.buffer.load.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.ll [AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics 2018-10-03 10:29:43 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.ll [AMDGPU] Allow int types for MUBUF vdata 2018-08-21 11:08:12 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.load.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.store.d16.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.store.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.tbuffer.load.d16.ll AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature. 2018-02-01 18:41:33 +00:00
llvm.amdgcn.tbuffer.load.ll [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
llvm.amdgcn.tbuffer.store.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.tbuffer.store.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.trig.preop.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
llvm.amdgcn.ubfe.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
llvm.amdgcn.udot2.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.udot4.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.udot8.ll AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
llvm.amdgcn.unreachable.ll Fix test from polluting the source tree 2017-04-22 07:53:40 +00:00
llvm.amdgcn.update.dpp.ll [AMDGPU]: Turn on the DPP combiner by default 2018-12-05 15:21:17 +00:00
llvm.amdgcn.wave.barrier.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.amdgcn.workgroup.id.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.workitem.id.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.wqm.vote.ll AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
llvm.amdgcn.writelane.ll AMDGPU: Fix getInstSizeInBytes 2018-08-29 07:46:09 +00:00
llvm.ceil.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.cos.f16.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.cos.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.dbg.value.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.exp2.f16.ll [AMDGPU] Fixed some instructions latencies 2018-03-30 16:19:13 +00:00
llvm.exp2.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
llvm.floor.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.fma.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.fmuladd.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log2.f16.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
llvm.log2.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
llvm.log10.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log10.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.maxnum.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
llvm.memcpy.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
llvm.minnum.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
llvm.pow.ll
…
llvm.r600.cube.ll
…
llvm.r600.dot4.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.r600.group.barrier.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.r600.read.local.size.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.r600.recipsqrt.clamped.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.r600.recipsqrt.ieee.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.r600.tex.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.rint.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.rint.f64.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
llvm.rint.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.round.f64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
llvm.round.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
llvm.sin.f16.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.sin.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.sqrt.f16.ll [AMDGPU] Fixed some instructions latencies 2018-03-30 16:19:13 +00:00
llvm.trunc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-constant-f32.ll [AMDGPU] Increased vector length for global/constant loads. 2018-03-07 17:09:18 +00:00
load-constant-f64.ll [AMDGPU] Increased vector length for global/constant loads. 2018-03-07 17:09:18 +00:00
load-constant-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-constant-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-constant-i16.ll AMDGPU: Fix selection error on constant loads with < 4 byte alignment 2018-03-29 19:59:28 +00:00
load-constant-i32.ll [AMDGPU] Split v32i32 loads 2018-08-31 22:43:36 +00:00
load-constant-i64.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
load-global-f32.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
load-global-f64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
load-global-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-global-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-global-i16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-global-i32.ll [AMDGPU] Split v32i32 loads 2018-08-31 22:43:36 +00:00
load-global-i64.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
load-hi16.ll AMDGPU: Add D16 instructions preserve unused bits feature 2018-05-04 20:06:57 +00:00
load-input-fold.ll
…
load-lo16.ll Implement computeKnownBits for scalar_to_vector 2018-11-19 23:34:07 +00:00
load-local-f32-no-ds128.ll AMDGPU: Add a missing test for the 128-bit local addr space option 2018-05-15 21:41:57 +00:00
load-local-f32.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-f64.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-local-i8.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-local-i16.ll [SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes 2018-10-30 10:32:11 +00:00
load-local-i32.ll [AMDGPU] Split v32i32 loads 2018-08-31 22:43:36 +00:00
load-local-i64.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-select-ptr.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-weird-sizes.ll [AMDGPU] Prevent post-RA scheduler from breaking memory clauses 2017-09-19 20:54:38 +00:00
local-64.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
local-atomics.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
local-atomics64.ll Bias physical register immediate assignments 2018-11-14 21:11:53 +00:00
local-memory.amdgcn.ll [AMDGPU] Generate range metadata for workitem id 2017-04-12 20:48:56 +00:00
local-memory.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
local-memory.r600.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
local-stack-slot-offset.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
loop-address.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
loop-idiom.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
loop_break.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
loop_exit_with_xor.ll [AMDGPU] Fixed incorrect break from loop 2018-05-25 07:55:04 +00:00
lower-kernargs.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
lower-mem-intrinsics.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
lower-range-metadata-intrinsic-call.ll [AMDGPU] Generate range metadata for workitem id 2017-04-12 20:48:56 +00:00
lshl64-to-32.ll [AMDGPU] computeKnownBitsForTargetNode for 24 bit mul 2017-08-28 16:35:37 +00:00
lshr.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
macro-fusion-cluster-vcc-uses.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
mad-combine.ll AMDGPU: Fix -enable-var-scope violations 2017-11-12 23:53:44 +00:00
mad-mix-hi.ll AMDGPU: Remove custom BUILD_VECTOR combine 2018-10-30 01:37:59 +00:00
mad-mix-lo.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
mad-mix.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
mad24-get-global-id.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
mad_64_32.ll [AMDGPU] Fixed some instructions latencies 2018-03-30 16:19:13 +00:00
mad_int24.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
mad_uint24.ll AMDGPU: Remove broken i16 ternary patterns 2018-08-07 21:54:37 +00:00
madak-inline-constant.mir [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32. 2018-09-10 16:42:49 +00:00
madak.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
madmk.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
max-literals.ll
…
max.i16.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
max.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
max3.ll AMDGPU: Fix min3/max3 combines for f16/i16 2017-05-17 19:25:06 +00:00
mem-builtins.ll AMDGPU: Remove error on calls for amdgcn 2017-08-03 23:24:05 +00:00
memory-legalizer-amdpal.ll [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D. 2018-12-10 16:35:53 +00:00
memory-legalizer-atomic-cmpxchg.ll [AMDGPU] Cleanup in memory legalizer tests. NFC. 2018-02-13 20:03:32 +00:00
memory-legalizer-atomic-fence.ll [AMDGPU] Cleanup in memory legalizer tests. NFC. 2018-02-13 20:03:32 +00:00
memory-legalizer-atomic-insert-end.mir AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
memory-legalizer-atomic-rmw.ll [AMDGPU] Cleanup in memory legalizer tests. NFC. 2018-02-13 20:03:32 +00:00
memory-legalizer-invalid-addrspace.mir [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-invalid-syncscope.ll [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-load.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
memory-legalizer-local.mir [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-mesa3d.ll [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D. 2018-12-10 16:35:53 +00:00
memory-legalizer-multiple-mem-operands-atomics.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
memory-legalizer-region.mir [AMDGPU] Simplify memory legalizer 2018-06-07 22:28:32 +00:00
memory-legalizer-store-infinite-loop.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
memory-legalizer-store.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
memory_clause.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
memory_clause.mir AMDGPU: Turn D16 for MIMG instructions into a regular operand 2018-06-21 13:36:01 +00:00
merge-load-store-physreg.mir AMDGPU: Track physreg uses in SILoadStoreOptimizer 2018-02-23 10:45:56 +00:00
merge-load-store-vreg.mir [AMDGPU] Fix ds combine with subregs 2018-09-25 23:33:18 +00:00
merge-load-store.mir AMDGPU: Fix incorrect reordering when inline asm defines LDS address 2018-02-08 01:56:14 +00:00
merge-m0.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
merge-store-crash.ll [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
merge-store-usedef.ll [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
merge-stores.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
mesa_regression.ll
…
min.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
min3.ll AMDGPU: Fix min3/max3 combines for f16/i16 2017-05-17 19:25:06 +00:00
misched-killflags.mir [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
missing-store.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mode-register.mir [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
move-addr64-rsrc-dead-subreg-writes.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
move-to-valu-atomicrmw.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
move-to-valu-worklist.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
movreld-bug.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
movrels-bug.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
mubuf-legalize-operands.ll [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions 2018-10-08 18:47:01 +00:00
mubuf-legalize-operands.mir [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions 2018-10-08 18:47:01 +00:00
mubuf-offset-private.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
mubuf-shader-vgpr.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
mubuf.ll AMDGPU: Remove llvm.SI.buffer.load.dword 2018-12-07 17:46:20 +00:00
mul.i16.ll AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on calls 2018-07-31 19:17:47 +00:00
mul.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
mul_int24.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul_uint24-amdgcn.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul_uint24-r600.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
multi-divergent-exit-region.ll Bias physical register immediate assignments 2018-11-14 21:11:53 +00:00
multilevel-break.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
nand.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
nested-calls.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
nested-loop-conditions.ll AMDGPU: Remove PHI loop condition optimization 2018-10-31 13:26:48 +00:00
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
no-shrink-extloads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
noop-shader-O0.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
nop-data.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
nor.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
not-scalarize-volatile-load.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
nullptr.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
omod-nsz-flag.mir AMDGPU: Check NSZ MI flag when folding omod 2018-08-12 08:44:25 +00:00
omod.ll AMDGPU: Keep track of modifiers when converting v_mac to v_mad 2017-03-11 05:40:40 +00:00
opencl-image-metadata.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
operand-folding.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
operand-spacing.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
opt-sgpr-to-vgpr-copy.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
optimize-if-exec-masking.mir Fix MachineInstr::findRegisterUseOperandIdx subreg checks 2018-11-12 18:12:28 +00:00
optimize-negated-cond-exec-masking.mir [AMDGPU] Simplify negated condition 2018-12-13 03:17:40 +00:00
optimize-negated-cond.ll [AMDGPU] Simplify negated condition 2018-12-13 03:17:40 +00:00
or.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
or3.ll AMDGPU: Generate VALU ThreeOp Integer instructions 2018-12-06 14:33:40 +00:00
over-max-lds-size.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
pack.v2f16.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
pack.v2i16.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
packed-op-sel.ll AMDGPU: Select DS insts without m0 initialization 2017-11-29 00:55:57 +00:00
packetizer.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
parallelandifcollapse.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
parallelorifcollapse.ll fix typos in comments; NFC 2017-07-16 08:11:56 +00:00
partial-sgpr-to-vgpr-spills.ll RegAllocFast: Leave unassigned virtreg entries in map 2018-11-07 06:57:03 +00:00
partial-shift-shrink.ll AMDGPU: Handle partial shift reduction for variable shifts 2018-05-09 20:52:54 +00:00
partially-dead-super-register-immediate.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
perfhint.ll [AMDGPU] Do not consider indirect acces through phi for wave limiter 2018-06-11 16:50:49 +00:00
permute.ll [AMDGPU] Corrected computeKnownBits for V_PERM_B32 2018-06-13 18:52:54 +00:00
phi-elimination-assertion.mir [PHIElimination] Lower a PHI node with only undef uses as IMPLICIT_DEF 2018-09-30 17:26:58 +00:00
pk_max_f16_literal.ll [AMDGPU] Truncate packed inline constant 2018-04-24 18:17:55 +00:00
postra-norename.mir [MachineOperand][Target] MachineOperand::isRenamable semantics changes 2018-02-23 18:25:08 +00:00
predicate-dp4.ll
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predicates.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
print-mir-custom-pseudo.ll [AMDGPU] Rename pass "isel" to "amdgpu-isel" 2018-10-03 03:38:22 +00:00
private-access-no-objects.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
private-element-size.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
private-memory-atomics.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
private-memory-r600.ll AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements 2018-02-16 19:14:17 +00:00
promote-alloca-addrspacecast.ll
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promote-alloca-array-aggregate.ll AMDGPU: Fix assert on alloca of array of struct 2017-09-14 18:02:29 +00:00
promote-alloca-array-allocation.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
promote-alloca-bitcast-function.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
promote-alloca-calling-conv.ll AMDGPU: Increase default stack alignment 2018-03-29 20:22:04 +00:00
promote-alloca-globals.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
promote-alloca-invariant-markers.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
promote-alloca-lifetime.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
promote-alloca-mem-intrinsics.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
promote-alloca-no-opts.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
promote-alloca-padding-size-estimate.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
promote-alloca-stored-pointer-value.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
promote-alloca-to-lds-icmp.ll AMDGPU: Add an option -disable-promote-alloca-to-lds 2018-11-06 21:28:17 +00:00
promote-alloca-to-lds-phi.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
promote-alloca-to-lds-select.ll AMDGPU: Fix using old address spaces in some tests 2018-12-05 17:34:59 +00:00
promote-alloca-unhandled-intrinsic.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
promote-alloca-vector-to-vector.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
promote-alloca-volatile.ll AMDGPU/SI: Don't promote to vector if the load/store is volatile. 2017-05-12 20:31:12 +00:00
promote-constOffset-to-imm.ll [AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions. 2018-12-14 21:13:14 +00:00
promote-constOffset-to-imm.mir [AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions. 2018-12-14 21:13:14 +00:00
pv-packing.ll
…
pv.ll
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r600-constant-array-fixup.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
r600-encoding.ll
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r600-export-fix.ll
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r600-infinite-loop-bug-while-reorganizing-vector.ll
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r600-legalize-umax-bug.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
r600.alu-limits.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
r600.amdgpu-alias-analysis.ll AMDGPU: Fix r600 test 2018-09-11 04:39:16 +00:00
r600.bitcast.ll [AMDGPU] Add INDIRECT_BASE_ADDR to R600_Reg32 class (PR33045) 2017-05-23 21:27:15 +00:00
r600.extract-lowbits.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
r600.func-alignment.ll AMDGPU/R600: Make sure functions are cacheline aligned 2018-05-31 04:08:08 +00:00
r600.global_atomics.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
r600.private-memory.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
r600.work-item-intrinsics.ll AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS 2018-08-01 18:36:07 +00:00
r600cfg.ll
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rcp-pattern.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
rcp_iflag.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
read-register-invalid-subtarget.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
read-register-invalid-type-i32.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
read-register-invalid-type-i64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
read_register.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
readcyclecounter.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
readlane_exec0.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
reduce-build-vec-ext-to-ext-build-vec.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
reduce-load-width-alignment.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
reduce-saveexec.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
reduce-store-width-alignment.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
reduction.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
reg-coalescer-sched-crash.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
regcoal-subrange-join-seg.mir Shrink interval after moving copy in removePartialRedundancy 2018-06-18 17:16:39 +00:00
regcoal-subrange-join.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
regcoalesce-dbg.mir MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
regcoalesce-prune.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
regcoalescing-remove-partial-redundancy-assert.mir [RegisterCoalescer] Fix for assert in removePartialRedundancy 2018-08-23 17:28:33 +00:00
register-count-comments.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
rename-disconnected-bug.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
rename-independent-subregs-mac-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
rename-independent-subregs.mir RenameIndependentSubregs: Fix handling of undef tied operands 2018-07-09 20:07:03 +00:00
reorder-stores.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
reqd-work-group-size.ll AMDGPU: Add pass to optimize reqd_work_group_size 2018-05-18 21:35:00 +00:00
ret.ll Bias physical register immediate assignments 2018-11-14 21:11:53 +00:00
ret_jump.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
rewrite-out-arguments-address-space.ll AMDGPU: Look through a bitcast user of an out argument 2017-07-28 19:06:16 +00:00
rewrite-out-arguments.ll [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
rotl.i64.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
rotl.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
rotr.i64.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
rotr.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
rsq.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
rv7x0_count3.ll
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s_addk_i32.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
s_movk_i32.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
s_mulk_i32.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
sad.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
saddo.ll AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
salu-to-valu.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
sampler-resource-id.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
scalar-branch-missing-and-exec.ll AMDGPU: Bring processors and features in sync with the spec 2018-02-16 21:26:25 +00:00
scalar-store-cache-flush.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
scalar_to_vector.ll AMDGPU: Fix scalar_to_vector for v4i16/v4f16 2018-06-20 19:45:48 +00:00
scalar_to_vector_v2x16.ll [AMDGPU] Restored selection of scalar_to_vector (v2x16) 2018-11-19 19:58:13 +00:00
sched-crash-dbg-value.mir MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
schedule-fs-loop-nested-if.ll
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schedule-fs-loop-nested.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
schedule-fs-loop.ll
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schedule-global-loads.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
schedule-if-2.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
schedule-if.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
schedule-ilp.ll AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental) 2017-11-20 14:35:53 +00:00
schedule-kernel-arg-loads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
schedule-regpressure-limit2.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit3.ll [AMDGPU] Fix amdgpu-waves-per-eu accounting in scheduler 2018-05-12 01:41:56 +00:00
schedule-regpressure.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
schedule-vs-if-nested-loop-failure.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
schedule-vs-if-nested-loop.ll
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scheduler-subrange-crash.ll AMDGPU: Remove llvm.SI.buffer.load.dword 2018-12-07 17:46:20 +00:00
scratch-buffer.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
scratch-simple.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
sdiv.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
sdivrem24.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
sdivrem64.ll [AMDGPU] New 64 bit div/rem expansion 2017-10-06 17:24:45 +00:00
sdwa-gfx9.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sdwa-op64-test.ll [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos 2018-12-03 13:04:54 +00:00
sdwa-ops.mir [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos 2018-12-03 13:04:54 +00:00
sdwa-peephole-instr.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sdwa-peephole.ll AMDGPU: Fix various issues around the VirtReg2Value mapping 2018-11-30 22:55:29 +00:00
sdwa-preserve.mir [AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE. 2018-03-30 05:03:36 +00:00
sdwa-scalar-ops.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
sdwa-vop2-64bit.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
select-fabs-fneg-extract-legacy.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
select-fabs-fneg-extract.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
select-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
select-opt.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
select-undef.ll Moved dag-combine-select-undef.ll into amdgpu. NFC. 2018-11-17 00:17:15 +00:00
select-vectors.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
select.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
select.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
select64.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
selectcc-cnd.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
selectcc-cnde-int.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
selectcc-icmp-select-float.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
selectcc-opt.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
selectcc.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
sendmsg-m0-hazard.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
set-dx10.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
setcc-equivalent.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
setcc-fneg-constant.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
setcc-limit-load-shrink.ll Check shouldReduceLoadWidth from SimplifySetCC 2018-10-31 21:24:30 +00:00
setcc-opt.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
setcc-sext.ll [AMDGPU] Simplify setcc (sext from i1 b), -1|0, cc 2017-06-27 18:53:03 +00:00
setcc.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
setcc64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
seto.ll
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setuo.ll
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sext-eliminate.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
sext-in-reg-failure-r600.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
sext-in-reg.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
sgpr-control-flow.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
sgpr-copy-duplicate-operand.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
sgpr-copy.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
sgpr-spill-wrong-stack-id.mir AMDGPU: Cleanup / relax tests for future changes 2018-11-26 17:17:07 +00:00
sgprcopies.ll AMDGPU : Fix common dominator of two incoming blocks terminates with uniform branch issue. 2017-04-12 23:51:47 +00:00
shader-addr64-nonuniform.ll [AMDGPU] Avoid using divergent value in mubuf addr64 descriptor 2018-08-02 22:53:57 +00:00
shared-op-cycle.ll
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shift-and-i64-ubfe.ll AMDGPU: Fix -enable-var-scope violations 2017-11-12 23:53:44 +00:00
shift-and-i128-ubfe.ll AMDGPU: Cleanup subtarget features 2017-08-07 14:58:04 +00:00
shift-i64-opts.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
shift-i128.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
shl-add-to-add-shl.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
shl.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
shl.v2i16.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
shl_add.ll AMDGPU: Generate VALU ThreeOp Integer instructions 2018-12-06 14:33:40 +00:00
shl_add_constant.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
shl_add_ptr.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
shl_or.ll AMDGPU: Generate VALU ThreeOp Integer instructions 2018-12-06 14:33:40 +00:00
shrink-add-sub-constant.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
shrink-carry.mir [AMDGPU] Shrinking V_SUBBREV_U32 2018-02-24 01:32:32 +00:00
shrink-vop3-carry-out.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
si-annotate-cf-noloop.ll [AMDGPU] Eliminate no effect instructions before s_endpgm 2017-08-16 04:43:49 +00:00
si-annotate-cf-unreachable.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
si-annotate-cf.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
si-annotate-cfg-loop-assert.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
si-fix-sgpr-copies.mir AMDGPU: Don't leave dead illegal VGPR->SGPR copies 2018-03-19 14:07:15 +00:00
si-instr-info-correct-implicit-operands.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
si-lower-control-flow-kill.ll AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic 2018-04-24 21:37:57 +00:00
si-lower-control-flow-unreachable-block.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
si-lower-control-flow.mir AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
si-scheduler.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
si-sgpr-spill.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
si-spill-cf.ll AMDGPU: Remove SITypeRewriter 2017-06-28 21:38:50 +00:00
si-spill-sgpr-stack.ll AMDGPU: Use correct register names in inline assembly 2017-06-08 19:03:20 +00:00
si-triv-disjoint-mem-access.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
si-vector-hang.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
sibling-call.ll AMDGPU: Generate VALU ThreeOp Integer instructions 2018-12-06 14:33:40 +00:00
sign_extend.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
simplify-libcalls.ll [AMDGPU] Fix discarded result of addAttribute 2018-12-09 21:56:50 +00:00
simplifydemandedbits-recursion.ll Use the return value of UpdateNodeOperands(); in some cases, UpdateNodeOperands() modifies the node in-place and using the return value isn’t strictly necessary. However, it does not necessarily modify the node, but may return a resultant node if it already exists in the DAG. See comments in UpdateNodeOperands(). In that case, the return value must be used to avoid such scenarios as an infinite loop (node is assumed to have been updated, so added back to the worklist, and re-processed; however, node hasn’t changed so it is once again passed to UpdateNodeOperands(), assumed modified, added back to worklist; cycle infinitely repeats). 2017-10-16 23:38:53 +00:00
sint_to_fp.f64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
sint_to_fp.i64.ll [AMDGPU] Eliminate SGPR to VGPR copy when possible 2017-06-20 18:32:42 +00:00
sint_to_fp.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
sitofp.f16.ll [AMDGPU] Add instruction selection for i1 to f16 conversion 2018-09-19 16:32:12 +00:00
skip-if-dead.ll AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
smed3.ll AMDGPU: Additional pattern for i16 median3 matching 2018-11-14 20:10:41 +00:00
sminmax.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
sminmax.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
smrd-fold-offset.mir AMDGPU: Divergence-driven selection of scalar buffer load intrinsics 2018-11-30 22:55:38 +00:00
smrd-vccz-bug.ll AMDGPU/InsertWaitcnts: Untangle some semi-global state 2018-11-29 11:06:06 +00:00
smrd.ll AMDGPU: Allow f32 types for llvm.amdgcn.s.buffer.load 2018-12-07 18:41:39 +00:00
sopk-compares.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
spill-alloc-sgpr-init-bug.ll AMDGPU: Fix register name format in tests 2018-03-27 18:39:42 +00:00
spill-before-exec.mir [RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled 2018-09-25 18:37:38 +00:00
spill-cfg-position.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
spill-csr-frame-ptr-reg-copy.ll AMDGPU: Move a flawed assert when spilling SGPRs 2018-04-23 16:13:30 +00:00
spill-empty-live-interval.mir AMDGPU: Cleanup / relax tests for future changes 2018-11-26 17:17:07 +00:00
spill-m0.ll RegAllocFast: Leave unassigned virtreg entries in map 2018-11-07 06:57:03 +00:00
spill-offset-calculation.ll [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits 2018-07-26 19:47:51 +00:00
spill-scavenge-offset.ll AMDGPU: Use correct register names in inline assembly 2017-06-08 19:03:20 +00:00
spill-to-smem-m0.ll AMDGPU: M0 operands to spill/restore opcodes are dead 2017-06-27 08:04:13 +00:00
spill-wide-sgpr.ll Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
split-scalar-i64-add.ll CodeGen: Make computeRegisterLiveness consider successors 2018-08-30 07:17:51 +00:00
split-smrd.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
split-vector-memoperand-offsets.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
splitkit.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sra.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
srem.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
srl.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
ssubo.ll AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
stack-realign.ll AMDGPU: Support realigning stack 2018-03-29 21:30:06 +00:00
stack-size-overflow.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
stack-slot-color-sgpr-vgpr-spills.mir AMDGPU: Cleanup / relax tests for future changes 2018-11-26 17:17:07 +00:00
store-barrier.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
store-global.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
store-hi16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
store-local.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
store-private.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
store-v3i64.ll [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
store-vector-ptrs.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
store-weird-sizes.ll [SelectionDAG] Improve SimplifyDemandedBits to SimplifyDemandedVectorElts simplification 2018-12-01 12:08:55 +00:00
store_typed.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
stress-calls.ll Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
structurize.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
structurize1.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
sub.i16.ll AMDGPU: Replace i64 add/sub lowering 2017-11-15 21:51:43 +00:00
sub.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
sub.v2i16.ll [AMDGPU] Remove useless check from test. NFC. 2018-09-25 01:24:54 +00:00
sub_i1.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
subreg-coalescer-crash.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
subreg-coalescer-undef-use.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
subreg-eliminate-dead.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
subreg-intervals.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
subreg-split-live-in-error.mir [RegAllocGreedy] IMPLICIT_DEF values shouldn't prefer registers 2018-12-14 14:07:57 +00:00
subreg_interference.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
swizzle-export.ll
…
syncscopes.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
tail-call-cgp.ll AMDGPU: Start adding tail call support 2017-08-11 20:42:08 +00:00
target-cpu.ll AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements 2018-02-16 19:14:17 +00:00
tex-clause-antidep.ll
…
texture-input-merge.ll
…
trap.ll AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as 2018-05-29 19:09:13 +00:00
trunc-bitcast-vector.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
trunc-cmp-constant.ll AMDGPU: Fix -enable-var-scope violations 2017-11-12 23:53:44 +00:00
trunc-combine.ll AMDGPU: Fix assert in truncate combine with vectors 2018-07-12 19:40:16 +00:00
trunc-store-f64-to-f16.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
trunc-store-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
trunc-store.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
trunc-vector-store-assertion-failure.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
trunc.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
tti-unroll-prefs.ll AMDGPU: Remove -mcpu=SI 2017-08-07 18:30:35 +00:00
twoaddr-mad.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
uaddo.ll AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
udiv.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
udivrem.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
udivrem24.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
udivrem64.ll AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
uint_to_fp.f64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
uint_to_fp.i64.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
uint_to_fp.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
uitofp.f16.ll [AMDGPU] Add instruction selection for i1 to f16 conversion 2018-09-19 16:32:12 +00:00
umed3.ll AMDGPU: Additional pattern for i16 median3 matching 2018-11-14 20:10:41 +00:00
unaligned-load-store.ll DAG: Fix expansion of unaligned FP loads and stores 2018-09-13 12:14:23 +00:00
undefined-physreg-sgpr-spill.mir AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
undefined-subreg-liverange.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
unhandled-loop-condition-assertion.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
uniform-crash.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
uniform-loop-inside-nonuniform.ll [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556) 2018-04-25 12:32:46 +00:00
unify-metadata.ll
…
unigine-liveness-crash.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
unknown-processor.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
unpack-half.ll [SelectionDAG] Fixed f16-from-vector promotion problem 2018-01-09 21:36:25 +00:00
unroll.ll [AMDGPU] Unroll more to eliminate phis and conditions 2017-04-07 16:26:28 +00:00
unsupported-calls.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
unsupported-cc.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
urem.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
use-sgpr-multiple-times.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
usubo.ll AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
v1i64-kernel-arg.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
v_cndmask.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
v_cvt_pk_u8_f32.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
v_mac.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
v_mac_f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
v_madak_f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
v_swap_b32.mir [AMDGPU] Match v_swap_b32 2018-10-29 17:26:01 +00:00
valu-i1.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
vccz-corrupt-bug-workaround.mir AMDGPU/InsertWaitcnts: Untangle some semi-global state 2018-11-29 11:06:06 +00:00
vector-alloca-addrspacecast.ll AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction. 2018-05-11 22:17:57 +00:00
vector-alloca-atomic.ll AMDGPU/SI: Don't promote alloca to vector for atomic load/store 2018-05-17 21:49:44 +00:00
vector-alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
vector-extract-insert.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
vector-legalizer-divergence.ll [CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands 2018-06-04 20:19:45 +00:00
vectorize-global-local.ll [AMDGPU] Switch scalarize global loads ON by default 2017-07-04 17:32:00 +00:00
verifier-implicit-virtreg-invalid-physreg-liveness.mir MachineVerifier: Fix assert on implicit virtreg use 2018-08-27 17:40:09 +00:00
verifier-pseudo-terminators.mir AMDGPU: Fix analyzeBranch failing with pseudoterminators 2018-11-16 05:03:02 +00:00
vertex-fetch-encoding.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
vgpr-spill-emergency-stack-slot-compute.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
vgpr-spill-emergency-stack-slot.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
vi-removed-intrinsics.ll Reapply "Adapt gcov to changes in CFE." 2018-12-06 18:44:48 +00:00
vop-shrink-frame-index.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
vop-shrink-non-ssa.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vop-shrink.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
vselect.ll AMDGPU: Add macro fusion schedule DAG mutation 2017-07-06 20:57:05 +00:00
vselect64.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
vtx-fetch-branch.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
vtx-schedule.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
wait.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
waitcnt-back-edge-loop.mir [AMDGPU][Waitcnt] Fix handling of loops with many bottom blocks 2018-05-30 15:47:45 +00:00
waitcnt-debug.mir [AMDGPU] Waitcnt pass: add debug options 2018-04-25 19:21:26 +00:00
waitcnt-flat.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
waitcnt-loop-irreducible.mir AMDGPU/InsertWaitcnts: Remove the dependence on MachineLoopInfo 2018-11-29 11:06:26 +00:00
waitcnt-loop-single-basic-block.mir [AMDGPU] Waitcnt pass: Modify the waitcnt pass to propagate info in the case of a single basic block loop. mergeInputScoreBrackets() does this for us; update it so that it processes the single bb's score bracket when processing the single bb's preds. It is, after all, a pred of itself, so it's score bracket is needed. 2018-03-14 22:04:32 +00:00
waitcnt-looptest.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
waitcnt-no-redundant.mir [AMDGPU] Make note of existing waitcnt instrs; this is add-on work related to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up. 2018-02-19 19:19:59 +00:00
waitcnt-permute.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
waitcnt-preexisting.mir AMDGPU/InsertWaitcnts: Untangle some semi-global state 2018-11-29 11:06:06 +00:00
waitcnt.mir [AMDGPU][Waitcnt] Fix handling of flat instrs 2018-06-04 16:51:59 +00:00
wave_dispatch_regs.ll [AMDGPU] Ensure there are enough registers for wave dispatch 2018-04-11 17:18:36 +00:00
widen-smrd-loads.ll AMDGPU: Try a lot harder to emit scalar loads 2018-06-07 09:54:49 +00:00
widen-vselect-and-mask.ll DAG: Fix creating select with wrong condition type 2017-10-25 07:14:07 +00:00
widen_extending_scalar_loads.ll AMDGPU: Preserve metadata when widening loads 2018-06-05 19:52:56 +00:00
wqm.ll AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
wqm.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
write-register-vgpr-into-sgpr.ll [AMDGPU] Eliminate no effect instructions before s_endpgm 2017-08-16 04:43:49 +00:00
write_register.ll [AMDGPU] Eliminate no effect instructions before s_endpgm 2017-08-16 04:43:49 +00:00
wrong-transalu-pos-fix.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
xfail.r600.bitcast.ll AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
xnor.ll [AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XOR 2018-12-01 12:27:53 +00:00
xor.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
xor_add.ll AMDGPU: Generate VALU ThreeOp Integer instructions 2018-12-06 14:33:40 +00:00
zero_extend.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
zext-i64-bit-operand.ll AMDGPU: Allow SIShrinkInstructions to work in non-SSA 2017-07-10 19:53:57 +00:00
zext-lid.ll [SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt 2018-10-31 19:57:36 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.