forked from OSchip/llvm-project
165 lines
4.2 KiB
YAML
165 lines
4.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-remove-short-exec-branches -amdgpu-skip-threshold=10 -verify-machineinstrs %s -o - | FileCheck %s
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# Make sure mandatory skips are not removed around mode defs.
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# FIXME: -amdgpu-skip-threshold seems to be backwards.
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---
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name: need_skip_setreg_imm32_b32
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body: |
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; CHECK-LABEL: name: need_skip_setreg_imm32_b32
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode
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; CHECK: bb.2:
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; CHECK: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode
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bb.2:
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S_ENDPGM 0
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...
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---
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name: need_skip_setreg_b32
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body: |
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; CHECK-LABEL: name: need_skip_setreg_b32
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode
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; CHECK: bb.2:
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; CHECK: S_ENDPGM 0
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bb.0:
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liveins: $sgpr0
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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liveins: $sgpr0
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode
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bb.2:
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S_ENDPGM 0
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...
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---
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name: need_skip_denorm_mode
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body: |
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; CHECK-LABEL: name: need_skip_denorm_mode
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: S_DENORM_MODE 3, implicit-def $mode, implicit $mode
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; CHECK: bb.2:
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; CHECK: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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S_DENORM_MODE 3, implicit-def $mode, implicit $mode
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bb.2:
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S_ENDPGM 0
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...
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---
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name: need_skip_round_mode
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body: |
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; CHECK-LABEL: name: need_skip_round_mode
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: S_ROUND_MODE 3, implicit-def $mode, implicit $mode
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; CHECK: bb.2:
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; CHECK: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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S_ROUND_MODE 3, implicit-def $mode, implicit $mode
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bb.2:
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S_ENDPGM 0
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...
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---
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name: need_skip_writelane_b32
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body: |
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; CHECK-LABEL: name: need_skip_writelane_b32
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: $sgpr0 = IMPLICIT_DEF
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; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0
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; CHECK: bb.2:
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; CHECK: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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$sgpr0 = IMPLICIT_DEF
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$vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0
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bb.2:
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S_ENDPGM 0
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...
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---
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name: need_skip_readlane_b32
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body: |
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; CHECK-LABEL: name: need_skip_readlane_b32
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: $vgpr0 = IMPLICIT_DEF
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; CHECK: $sgpr0 = V_READLANE_B32 $vgpr0, 0
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; CHECK: bb.2:
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; CHECK: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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$vgpr0 = IMPLICIT_DEF
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$sgpr0 = V_READLANE_B32 $vgpr0, 0
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bb.2:
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S_ENDPGM 0
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...
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