forked from OSchip/llvm-project
203 lines
7.2 KiB
LLVM
203 lines
7.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
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; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
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define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {
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; SI-LABEL: infinite_loop:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: BB0_1: ; %loop
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_branch BB0_1
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; IR-LABEL: @infinite_loop(
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; IR-NEXT: entry:
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; IR-NEXT: br label [[LOOP:%.*]]
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; IR: loop:
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; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
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; IR-NEXT: br label [[LOOP]]
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entry:
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br label %loop
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loop:
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store volatile i32 999, i32 addrspace(1)* %out, align 4
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br label %loop
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}
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define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) {
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; SI-LABEL: infinite_loop_ret:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; SI-NEXT: s_cbranch_execz BB1_3
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; SI-NEXT: ; %bb.1: ; %loop.preheader
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_and_b64 vcc, exec, -1
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; SI-NEXT: BB1_2: ; %loop
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccnz BB1_2
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; SI-NEXT: BB1_3: ; %UnifiedReturnBlock
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loop_ret(
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; IR-NEXT: entry:
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; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1
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; IR-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
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; IR: loop:
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; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
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; IR-NEXT: br i1 true, label [[LOOP]], label [[UNIFIEDRETURNBLOCK]]
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; IR: UnifiedReturnBlock:
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; IR-NEXT: ret void
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond = icmp eq i32 %tmp, 1
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br i1 %cond, label %loop, label %return
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loop:
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store volatile i32 999, i32 addrspace(1)* %out, align 4
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br label %loop
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return:
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ret void
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}
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define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
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; SI-LABEL: infinite_loops:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: s_mov_b64 s[2:3], -1
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; SI-NEXT: s_cbranch_scc1 BB2_4
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; SI-NEXT: ; %bb.1:
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x378
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; SI-NEXT: s_and_b64 vcc, exec, -1
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; SI-NEXT: BB2_2: ; %loop2
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccnz BB2_2
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; SI-NEXT: ; %bb.3: ; %Flow
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; SI-NEXT: s_mov_b64 s[2:3], 0
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; SI-NEXT: BB2_4: ; %Flow2
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; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccz BB2_7
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; SI-NEXT: ; %bb.5:
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt expcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_and_b64 vcc, exec, 0
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; SI-NEXT: BB2_6: ; %loop1
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccz BB2_6
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; SI-NEXT: BB2_7: ; %DummyReturnBlock
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loops(
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; IR-NEXT: entry:
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; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]]
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; IR: loop1:
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; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
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; IR-NEXT: br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]]
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; IR: loop2:
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; IR-NEXT: store volatile i32 888, i32 addrspace(1)* [[OUT]], align 4
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; IR-NEXT: br i1 true, label [[LOOP2]], label [[DUMMYRETURNBLOCK]]
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; IR: DummyReturnBlock:
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; IR-NEXT: ret void
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entry:
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br i1 undef, label %loop1, label %loop2
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loop1:
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store volatile i32 999, i32 addrspace(1)* %out, align 4
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br label %loop1
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loop2:
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store volatile i32 888, i32 addrspace(1)* %out, align 4
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br label %loop2
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}
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define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) {
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; SI-LABEL: infinite_loop_nest_ret:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; SI-NEXT: s_cbranch_execz BB3_5
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; SI-NEXT: ; %bb.1: ; %outer_loop.preheader
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; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 3, v0
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: BB3_2: ; %outer_loop
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; SI-NEXT: ; =>This Loop Header: Depth=1
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; SI-NEXT: ; Child Loop BB3_3 Depth 2
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; SI-NEXT: s_mov_b64 s[2:3], 0
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; SI-NEXT: BB3_3: ; %inner_loop
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; SI-NEXT: ; Parent Loop BB3_2 Depth=1
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; SI-NEXT: ; => This Inner Loop Header: Depth=2
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; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1]
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; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
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; SI-NEXT: s_waitcnt expcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
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; SI-NEXT: s_cbranch_execnz BB3_3
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; SI-NEXT: ; %bb.4: ; %loop.exit.guard
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; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1
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; SI-NEXT: s_or_b64 exec, exec, s[2:3]
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; SI-NEXT: s_mov_b64 vcc, 0
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; SI-NEXT: s_branch BB3_2
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; SI-NEXT: BB3_5: ; %UnifiedReturnBlock
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loop_nest_ret(
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; IR-NEXT: entry:
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; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; IR-NEXT: [[COND1:%.*]] = icmp eq i32 [[TMP]], 1
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; IR-NEXT: br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
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; IR: outer_loop:
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; IR-NEXT: br label [[INNER_LOOP:%.*]]
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; IR: inner_loop:
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; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
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; IR-NEXT: [[COND3:%.*]] = icmp eq i32 [[TMP]], 3
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; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]]
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; IR: TransitionBlock:
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; IR-NEXT: br i1 [[COND3]], label [[INNER_LOOP]], label [[OUTER_LOOP]]
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; IR: UnifiedReturnBlock:
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; IR-NEXT: ret void
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond1 = icmp eq i32 %tmp, 1
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br i1 %cond1, label %outer_loop, label %return
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outer_loop:
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; %cond2 = icmp eq i32 %tmp, 2
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; br i1 %cond2, label %outer_loop, label %inner_loop
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br label %inner_loop
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inner_loop: ; preds = %LeafBlock, %LeafBlock1
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store volatile i32 999, i32 addrspace(1)* %out, align 4
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%cond3 = icmp eq i32 %tmp, 3
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br i1 %cond3, label %inner_loop, label %outer_loop
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return:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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