llvm-project/llvm/test/CodeGen/AMDGPU/fold_16bit_imm.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass peephole-opt -o - %s | FileCheck -check-prefix=GCN %s
---
name: fold_simm_16_sub_to_lo
body: |
bb.0:
; GCN-LABEL: name: fold_simm_16_sub_to_lo
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
; GCN: [[COPY:%[0-9]+]]:sgpr_lo16 = COPY killed [[S_MOV_B32_]].lo16
; GCN: SI_RETURN_TO_EPILOG [[COPY]]
%0:sreg_32 = S_MOV_B32 2048
%1:sgpr_lo16 = COPY killed %0.lo16
SI_RETURN_TO_EPILOG %1
...
---
name: fold_simm_16_sub_to_phys
body: |
bb.0:
; GCN-LABEL: name: fold_simm_16_sub_to_phys
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
; GCN: $sgpr0 = S_MOV_B32 2048
; GCN: SI_RETURN_TO_EPILOG $sgpr0_lo16
%0:sreg_32 = S_MOV_B32 2048
$sgpr0_lo16 = COPY killed %0.lo16
SI_RETURN_TO_EPILOG $sgpr0_lo16
...
---
name: fold_aimm_16_sub_to_phys
body: |
bb.0:
; GCN-LABEL: name: fold_aimm_16_sub_to_phys
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: $agpr0 = V_ACCVGPR_WRITE_B32 0, implicit $exec
; GCN: SI_RETURN_TO_EPILOG $agpr0_lo16
%0:sreg_32 = S_MOV_B32 0
$agpr0_lo16 = COPY killed %0.lo16
SI_RETURN_TO_EPILOG $agpr0_lo16
...
---
name: fold_vimm_16_sub_to_lo
body: |
bb.0:
; GCN-LABEL: name: fold_vimm_16_sub_to_lo
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
; GCN: [[COPY:%[0-9]+]]:vgpr_lo16 = COPY killed [[S_MOV_B32_]].lo16
; GCN: SI_RETURN_TO_EPILOG [[COPY]]
%0:sreg_32 = S_MOV_B32 2048
%1:vgpr_lo16 = COPY killed %0.lo16
SI_RETURN_TO_EPILOG %1
...
---
name: fold_vimm_16_sub_to_phys
body: |
bb.0:
; GCN-LABEL: name: fold_vimm_16_sub_to_phys
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
; GCN: $vgpr0_lo16 = COPY killed [[S_MOV_B32_]].lo16
; GCN: SI_RETURN_TO_EPILOG $vgpr0_lo16
%0:sreg_32 = S_MOV_B32 2048
$vgpr0_lo16 = COPY killed %0.lo16
SI_RETURN_TO_EPILOG $vgpr0_lo16
...